Comparative experimental study of junctionless and inversion-mode nanowire transistors for analog applications

HAL Id: hal-02969748

https://hal.archives-ouvertes.fr/hal-02969748

Submitted on 27 Dec 2020

HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci- entific research documents, whether they are pub- lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers.

L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Comparative experimental study of junctionless and inversion-mode nanowire transistors for analog

applications

Daphnée Bosch, J.P. Colinge, J. Lugo, A. Tataridou, Christoforos Theodorou, X. Garros, S. Barraud, J. Lacord, B. Sklenard, M. Casse, et al.

To cite this version:

Daphnée Bosch, J.P. Colinge, J. Lugo, A. Tataridou, Christoforos Theodorou, et al.. Comparative experimental study of junctionless and inversion-mode nanowire transistors for analog applications.

2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Aug 2020,

Hsinchu, Taiwan. pp.126-127, �10.1109/VLSI-TSA48913.2020.9203690�. �hal-02969748�

Comparative experimental study of junctionless and inversion- mode nanowire transistors for analog applications

D. Bosch

^1,2

, J.P. Colinge

¹

, J. Lugo

¹

, A. Tataridou

²

, C. Theodorou

²

, X. Garros

¹

, S. Barraud

¹

, J. Lacord

¹

, B. Sklenard

¹

, M. Casse

¹

, L.

Brunet

¹

, P. Batude

¹

, C. Fenouillet-Béranger

¹

, D. Lattard

¹

, J. Cluzel

¹

, F. Allain

¹

, R. Nait Youcef

¹

, J.M. Hartmann

¹

, C. Vizioz

¹

, G.

Audoit

¹

, F. Balestra

²

, M. Vinet

¹

, F. Andrieu

¹

1

CEA-LETI, Univ. Grenoble Alpes, 17 rue des Martyrs, 38054 Grenoble, France ; email: [email protected]

2

Univ. Grenoble Alpes, IMEP-LAHC, 38000 Grenoble, France

Abstract— We fabricated JunctionLess (JL) and Inversion-Mode (IM) monocrystalline nanowire NMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junctionless transistors for analog applications:

AVT=1.4mV.µm matching, Av0=62dB gain (L=200nm), fT=126GHz cut-off frequency and f_MAX=182GHz maximum operating frequency.

Junctionless transistor performances even exceed those of IM-FETs in terms of back-bias capability, low-frequency noise, hot-carrier degradation and fMAX. This is explained by JL physics combining characterization and TCAD simulations: channel length modulation, bulk conduction and high channel depth sensitivity to back bias.

I. INTRODUCTION

Recent years have seen renewed interest for JL CMOS transistors because of the relative simplicity of its process integration and its potential fabrication at low temperature as a Back-End-Of-Line transistor for a 3D-sequential integration [1]. On the one hand, poly- crystalline silicon or germanium channels, whose doping is activated by a laser anneal, are a promising solution for low-cost and extremely- low-temperature fabrication [2, 3]. On the other hand, monocrystalline Si junctionless channels have already been demonstrated on either planar Silicon-On-Insulator (SOI) [4], FinFET [5] or nanowire architectures [6,7]. Furthermore, JL devices are attractive for analog applications since they are less prone to Hot Carrier Injection (HCI).

II. DEVICE PROCESS FLOW

We fabricated IM and JL nanowire nMOS down to W=20nm channel width and L=18nm gate length. The channel thickness is 11nm. The junctionless devices are made by epitaxially growing a 7nm thick in-situ phosphorous (P) doped Si film on a 4nm undoped SOI layer. Excellent crystalline quality is obtained (Fig.1). After full process integration the final channel doping level is uniform and equal to 10¹⁹ at/cm³. Such channel doping and thickness are optimized for planar devices. The fabrication process is outlined in Fig.2. All the devices feature the same gate stack with HfO2 dielectrics (equivalent oxide thickness EOT=1nm), TiN + poly-Si and identical 8nm thick spacer.

In order to assess the impact of the channel doping and the source/drain resistance, we added the same 17nm thick Raised Souce/Drain (RSD) and HDD+LDD doping processes for so-called Junctionless Accumulation Mode (JAM) transistors as for the IM reference (final anneal at 1050°C). Purely Junctionless transistors (named JL) have also been fabricated without doping under the spacer.

Instead, a 5keV P implantation in the 17nm thick RSD followed by a Solid Phase Epitaxy Regrowth (SPER) annealing at 525°C 30 min was carried out, in order to only dope the JL-RSD (see Kinetic Monte- Carlo profile on Fig.2) and avoid lateral doping diffusion. This process module is suitable for a 525°C 3D-sequential integration process [8].

III. DEVICE ELECTRICAL CHARACTERIZATION Digital I_ON-I_OFF figure of merit (Fig 3) show no significant difference between JAM and IM FET. Also, similar parasitic gate to SD capacitance C_GDS suggests a similar direct overlap controlled by the SD implant (Fig. 4). On the other hand, the JL FET has a 0.06fF/µm lower CGDS vs JAM/IM, which cannot be explained by the fringe components but rather by a depletion region extending below the spacers in JL transistors (Fig.5). Nevertheless JL devices suffers from higher access resistance (R0) due to non-optimized junctions (Fig 3).

Local variability: matching coefficient AVT is higher for JL/JAM devices than IM (1.7/1.4 vs. 1.0 mV.µm, Fig. 6). This degradation with the channel doping is attributed to Random Dopant Fluctuation [9].

Analog: we consider a nominal transistor width of W=0.24µm, (planar SOI configuration instead of a trigate nanowire structure). The JL/JAM subthreshold slope (SS) is SS=64mV/dec vs. 61mV/dec for the IM device (Fig. 7). However, back-bias can be leveraged in order to adjust the threshold voltage and tune performance [10]. Indeed, back-bias is more effective for wider than for narrower devices and it is more effective on JL/JAM than on IM transistors (Fig.8). Markedly, a negative back-bias applied on JAM moves the bulk conduction channel upwards towards the gate, which results in an improvement of the electrostatic control (SS, gd) and, therefore, improving gm/Id and g_m/g_d, as well as the Early voltage (V_EA) (Figs 9-10). As a result, JAM FETs reach analog performances that are slightly better than IM devices, up to an A_v0=68dB gain.

Reliability: we have performed Positive Bias Temperature Instability (PBTI) and Hot Carrier Injection (HCI) (Figs. 11-12). We demonstrate similar PBTI (88 years lifetime at VDD=0.8V) and even better HCI for JL as compared to IM. It can be explain by a lower and shifted to the drain (not underneath the gate dielectric as for IM/JAM) peak electric field.

Low-frequency drain current noise measurements (Fig.13) show a 31-die average 1/f signature and a slightly lower input-referred gate voltage noise level (SVg) for JAM. Using the Carrier number fluctuations with Correlated Mobility Fluctuations model [11] and taking into account the series resistance noise (S_Rsd), we fitted the normalized drain current noise at f =10 Hz (Fig.28) to extract the volumetric oxide effective trap density N_T, and the remote Coulomb scattering coefficient αsc for all wafers. We extracted a value of NT ≈ 7.5 10¹⁷ eV/cm³ for all cases, reflecting a similar interface quality, independently of the conduction mode. This value is also very close to state-of-the-art N_T values of high-k-metal-gate CMOS technologies [12]. Concerning αsc, a very similar value (≈ 4×10³ Vs/C) is extracted for all wafers, showing that the remote Coulomb scattering is not affected by the different conduction modes. Finally, SRsd has a significant impact only for JL, which can be linked to non-optimized source/drain doping [13].

Mobility differences, due to channel doping, are also translated into a cut-off frequency shift, measured at FT=130 GHz for JAM vs.

136 GHz for IM. But JAM exceeds IM devices in terms of FMAX

because of lower gate capacitances C_GDS. We demonstrate a record Fmax=182GHz for JAM nMOS (Fig 15).

IV. CONCLUSION

Finally, our devices feature record performance among junctionless nMOSFETs (Fig.16). Thanks to process technology variants, electrical characterizations and TCAD simulations, we demonstrated that such a technology offers a good tradeoff for mixed analog/digital applications.

REFERENCES

[1]A. Vandooren et al., TED, 2018. [2]J. Lin et al., EDL, 39, 9, p. 1326‑29, 2018. [3]D. Bosch et al., S3S, 2019. [4]C. Lee et al., TED, 2010. [5]T. K. Kim et al., EDL, 2013. [6]A. Veloso et al., VLSI, 2016. [7]S. Barraud et al, EDL, 2012 [8]J. Micout et al., S3S, 2017. [9] A. Kranti et al., ESSDERC, 2010 [10]R. Trevisoli et al., EUROSOI, 2015. [11] G. Ghibaudo et al., PSS,91. [12]

E.G. Ioannidis et al., SSE, 2014. [13] C. Diaz-Llorente et al., S3S, 2018 [14]A.

Vandooren et al., VLSI, 2018.

Fig.1: TEM cross section of JAM device. Excellent crystalline quality

is observed.

Fig.2: Detailed Process flow for IM (N+-i-N+), JAM (N+-N-N+) and JL

(N) devices.

Fig.3: ION-IOFF for L=35nm and W=20nm.

Fig.4: C(W) and CGDS extraction at L=35nm. Inset: Schematic with parasitic capacitance contributions.

Fig. 5 :

Electron density (SD cut) highlighting three operation regimes

Fig.6:

Pelgrom plot (local variability)

Fig.7: g_mMAX and SS as a function of L for W=0.24µm

Fig.8: Back bias efficiency for W=0.02µm and W=0.24µm.

Fig.9: g_d vs. L for V_B=0 and V_B=- 10V. VB<0 improves electrostatics.

Fig.10: Gain A_v0 for different Gate length. VB<0 improves Av0

Fig.11: Time-To-Failure for PBTI.

The 5-year criterion is met

Fig.12: Time-To-Failure for HCI.

The 5-year criterion is met.

Fig.13:Input-referred gate voltage power spectral density versus

frequency

Fig.14:Normalized drain current power spectral density versus I_D. Inset: Extracted values of N_t and α_sc

Fig.15: f_MAX and f_T comparison for different L.

Fig.16: nMOS junctionless benchmark for analog FOM ACKNOWLEDGMENTS:

This work was funded by French Public Authorities through the NANO2022, LabEx Minos ANR-10-LABX- 55-01& by the European Research Council (ERC) through My-CUBE project.

28nm 11nm 18nm

JAM

N BOX FDSOI G 1e20 at/cm3

S D

Spaceur 0

JAM IM JL

Silicides + Back-End-of-Line LDD + HDD + Spacer Raised SD

in-situdoped @ 2^e20 at/cm³ Active Zone definition + Gate stack (high-k dielectric)+ Spacer

SPER+ 525°C anneal

BOX FDSOI Si:P @1e19 at/cm³

BOX FDSOI

tSI=11nm

01020

Raised SD

CHANNEL

1E+19 Phosphorus profile (at/cm³)

Depth (nm)

5E+20

KMC

R0 (Ω.mm):

IM: 250 JAM: 260 JL: 6000 0 100 200 300 400 500 600 700 800 -12

-10 -8

-6

V

_DD

=0.8V JAM

IM JL

IOFF (A/µm)

I_ON (µA/µm)

L=35nm W=20nm

0 4 8 12

0 4 8

C (fF)

C

_OV

( fF/µm):

JAM: 0.48

IM: 0.49 JL: 0.42

W (µm)

VG=-0.5V L=35nm

0 25 50

0 50

100 A_VT=1.7mV.µm

AVT=1.4mV.µm JAM IM JL

VT (mV)

1/sqrt(W.L) (µm^-1) AVT=1mV.µm

V_D=0.8V

0,1 1

0 150 300

IM JAM JL

GmMAX (µS/µm)

L (µm) W=0.24µm N

_DIE

=28

40 60 80

SS (mV/dec)

0 1 100 200

VT (mV)

L (µm) IM

JL JAM

Solid: W=0,24µm Dot: W=0,02µm

VB=10V

0.1 1

10^-8 10^-7 10^-6 10^-5

W=0.24µm

gd (A/V)

L (µm)

JAM IM JL

solid V B=0 V open V

B=-10V

V

_DS

=0.8V

Gain A_V0(db)

V_B (V)

L=100 nm

L=200 nm

L=400 nm

IM

0 1 60 50

-10 18 65 53

JAM 0 1 12 51

-10 64.5 68.8 55

JL 0 59 47 38

-10 61.5 65 41

1 2 3

10^-11 10^-1 10⁹

TTF(s)

V

_G

(V) IM AC model

AC and IM:

V

_G-5y

=0.92V 88y @ V

_DD

=0.8V

L=0.1µm W=10µm

0.92 V

5 years

T=125°C

1 2 3

10^-11 10^-6 10^-1 10⁴ 10⁹

TTF (s)

V

_D

(V) JL IM JAM

model

W=240nm L=40nm

HCI, T=125°C V

_G-5y

~0.8V

10 100 1000

1E-12 1E-11 1E-10 1E-9

SVG (V²/Hz)

f (Hz) JAM IM JL V

_G

-V

_T

=0V

N

_DIES

=31 W= 240nm L= 110nm

10^-9 10^-8 10^-7 10^-6 10^-5 10^-9

10^-8 10^-7

0 2 4 6 8

SC (x10³)

N

_T(x10¹⁷)

/eV.cm³ V*s/C CNF+CMF SID/ID² (/Hz)

ID (A)

JAM IM JL

F=10Hz

30 40 50 60

120 160 200

F

_MAX

^JAM

IM

F (GHz)

L (nm) W=120nm N

_FINGER

=120

F

_T

Ref. [14] [6] This

Work Techno Low-Temp

FDSOI NW NW/FDS

OI

L_G(nm) 80 48 35

V_DD(V) 1.0 1.0 0.8

A_VT

(mV.µm) - 4.4 1.4

A_V0(dB) 55 for L=40nm

45 for L=80nm

68 for L=0.2µm f_T(GHz) 80 >70 126

fmax(GHz) 117 ~90 169

JL

G

in Drain region^Depletion

Bulk conduction

V

_G

<V

_TH

:

V

_TH

< V

_G

<V

_FB

:

V

_TH

< V

_FB

<V

_G

:

e

^-

density (cm

^-3

)

10

²¹

10

¹⁷

10

¹⁰

10

⁷

10

¹

Accumulation layer

(TCAD)

zz