DATA TERMINAL

- _ . _ - - - -

HP 13255 +21', MEMnRY MODULE

Manual Part No. 13255-91064

PRINT~D

AUG-Ol-76

DATA TERMINAL

TECHNICAL INFORMATION

- - - _ . _ - - - 1 HEWLETT 1I ^PACKARD

Printed in U.S.A.

132515

+2K Memorv MOdule 13255-91064/02

~ev AUG-01-76

t.o INTROnUCTTUN.

The +2K Memorv Morlule allows expansion of 264XX Data Terminal memory capacity. The read/write memorY 1s accessihle throuqh th~ t~rmlnal

bus and is orQanlzed in 2,048 by a-bit bytes. This memOrY module uses dynamic MOS RAM chips organized 4K by 1-bit in a 22-pin, dual-in-line packaqe.

2.0 OPERATI~G PAHAMFTFRS.

A summary of operatinq parameters for the t2K ~emory Module Is contalned in tables 1.0 thrnunh 5.0.

Ta~le 1.0 Physicol Parameters

--~---~---~---~---­~---

---

Part Size (L x W x 0) Weight

Mumber ~omenclature I +/-0.100 InChes I (Pounds)

============= ============================== =======================1=========

1

,

02640-60064 t?K M~morv peA 12.5 x 4.0 x 0.5 I 0.44 I

I I I

---~-~--- --~---~---~--- ---~---~---~---~----~---

~111mber of Backplane Slots Required:

---~--- --- ---~~--- ---

HP 13255 +2r:, MEMflRY MonUT.E

Manual Part No. 13255-91064

PP}NTF:D

AUG-Ol-76

~---~~-~---~~---~~~-~~~~---~-~---~-~~---~---~--~

NOTICF.

Top. information cont~ined in thI~ document Is suhject to change without notice.

HEWLETT-PACKARO MAKES ~O WARRANTY OF ANY KTNO WITH REGARD TO THIS MATER I A L, INCIJtJOT N~, BUT NnT L 1M T TF.D TO THF. 1MPL I EO WARRANTIE S OF

~ERC~A~TABTLTTY AND FITNESS FOP A PARTTCllLAR PURPOSE. Hewlett-Packard 5hAll not be liahle for ~rrors contained herein or for incidental or conseQuential damaqes in connection with the furnIshing, performance, Or use of this material.

This document contains proprietary information which is protected by

copvriQht. 1\11 riQhts are reserven. No part of this document may be

~hotocopied or reproduced without the orior written consent of Hewlett- Packard Company.

---- ^..

~---~---~---~---~~--~---~--~---~-~---~---CoPYright c 197f; by HF.wt,E.TT-PACKAPD COMPANY

NnTF.: This docum~nt is part of the 264XX DATA TERMINAL product series ^T~chnical Information Packaqe (HP 13255).

1325'i

+2K Memory Module 13255-91064/02

'Rev AUG-Ot-76

t.o

INTRODUCTTON.

The +2K Memory Morlule allows expansion of 264XX Data Terminal memory capacity. The readlwrite memorY is accessihle throuqh th~ t~rminal

bus and is orqanized in 2,048 by 8-bit bytes. Thts memorY module uses dynamic MOS RAM chips organized 4K by I-bit in a ?2-pin, dual-in-line pac1<aQe.

2.0 OPERATI~G PAHAMFTFRS.

A summary of operatinq parameters for the t2K ~emorY Module Is contained In tables 1.0 thrnunh 5.0.

Ta~le 1.0 Physical Parameters

---~---~-~---~---~---~---~---~---~

---

---~--- ---

Part Size (L x W x 0) Weight

Number ~omenclature I +1-0.100 InChes I (Pounds)

============= ==============================1=======================1=========

I I

I I

02640-60064 t?K Memorv peA I 12.5 x 4.0 x 0.5 I 0.44

t I

1 I

I I

I ,

1 t I I

---~---~---~--- ---~--- ---

~p 1 m b e r 0 f B a c 1< pIa n e S lot 5 R e qui ^t' e d :

---~---~---~---~--- ---~---~--- ---

13255

+2K ~emory Module 13255-91064/03

Fev AUG-01-76

Table 2.0 Reliability and Environmental Information

====::=============================:::===========================================

Envlronment~l: ( X ) BP Class B ( ) Other:

Restrictions: Tyoe tested at product level

--- ^..

---~---~---~~---~---~---

---

Fatlur~ Rate: 1.197 (percent per 1000 hours)

----

----.---~---~---

^..

---~---~-~-~---~---~---~---~-

Table 3.0 Power Supply and Clock Requirements - Measured (At +/-5% Hnless Otherwi~e Soecified)

----.---~-~-~---~---~---~---

---

_I

.~ Volt Supply +12 Volt Supply I -1? Volt Supply -42 Volt Supply I

@ 12n mA ~ 30 rnA I ~ 14 rnA @ ~A

I

I I I NOT APPLICABLE

===::==================================1=======================================

I

lt5 volts ac 1 220 volts ac

I

Q A I @ A

I

NOT APPLTCABLE t NOT APPLICAALE

--~.---~---~---~---~--~---

---

Clock Freouency: 4.915 ~Bz +/0.1%

---

---

13255 13255-Ql064/04

+2K Memorv Module Pev AUG-Ol-7b

Table 4.0 Jump~r DefinitIons

~---~---~-~---~---~---~-~---~---~-~---~---~---~-~­

----~~---~---~---~---

peA

Oesiqnation Tn

function

Out

---~-- ---~--- -~-~---

--- --- ---

- - - RAM S'l'l\HT ADD

?K Add 0 to start Andress Add 2K to start Address

of t.,odule. of ~odule.

4K Add 0 to start Address Add 4K to Start Address

of Module. of MOdule.

8K Add 0 to start Address Add 81<' to start Address

of Module. of Module.

16K Add 0 to start Address Add 16K to start Address

of 1-1odule. of Module.

3?K Add 0 to start Address Add 321<' to start Address

of Mndule. of Module.

(All in Is start (All out Is start Address of 0) Address of 62K)

================================================================================

t3?5~ 13255-91064/05

+2'< '~emOTV Modnle Pev AUG-01-76

5.0 Connector Information

================================================================================

CO'1nectC)T I Siqnal

and Pin No. I Marne

==============1================

P1, Pin 1 I +5V

I

-? I I

·-l I I

··4 I I

· .. 5 t I .-f; I t ,·7

,-~

.• q ,·10

' .. 1.2 -t3 -14 -15 -16 -17 -18

-19

-'0

-21 -22

SYS el.K

-12V ADORO AOOF1 ADDt<2

ADf)R3

AODR4 AODR5 ADDR6

AODRe

AIJDRto

ADOPt1 )DDR12 ADOR13 ADDR14 ADOR15

I/O GND

Signal Desc-riptlon

---~-~--~--~-~---~-~-~---

---

+5 Volt Power Supply

Ground rommon Return (Power and Siana]) 4.915 MHz System ClOCK

-12 Volt Power Supply

Negativp. Trlle, Address Bit 0 Negative True, Address Bit 1

N~qative True, Address Ait 2 Neqattve True, Address Ait 3

Negative True, Address Ait 4 Negative True, Address Bit s Negative True, Address Bit 6

Negativ~ True, Address Bit 7 Negative True, Address Bit 8 Negative True, Address Bit 9 Negative True, Address Ait

to

Negative True, Address Bit 11 Negative True, ~ddress Bit 12

N~gattve True, Address Bit 13 Negative True, Ad~ress Rit 14 Negative True, Address Bit 15

Negative True, Input Output/Memory Ground Common Return (Power and Signal)

================================================================================

t32~5 13255.Ql064/06

+2K ~emorv ModulE' Rev AUG-Ol-76

Table 5.0 Connector Information (Cont'd.)

~-~---~-~---~---~---~---~---~~---­

-~--- ---~---~--~--~---~---~---- ---

Connector and Pin No.

--- ---

P1, Pin l\

-e -n

-F;

-F'

-H

-T.I

-~

-p

-T

-u -v

-x -v

-7.

Signal Signal

~ame' Description

================1==============================================

~ND 1 Ground Common Return (Power and Slqnal) 1

I Not Uspd I

+t2V 1 +17 volt Power Supply

I

PWR 0» 'Systpm Power On

RUSO Neoative True, Data Aus

Rust

Neoative True, Data Rus

RUS2 Neqative True, Data Bus

BUS3 Neoative True, D.=ttfl Bus

AUS4 Neoative True, Data Bus

RUSS Neqatlve Tru~, Data Rus RUS6 NeQatlve True, Data Rus

RUS7 Neoative True, Data Aus

Ait 0

Ait 1 Alt 2 Rit 3

Bit 4

Rft 5 Bit n Ait 7

WPITE Neqative True, Write/Head Tyne Cvcle

~tot used

WAIT Neoative True, wait Control Line PRTOR IN Bus Controller Priority In

PRIOR OUT Rus Controller Priority Out

"'ot Used

RUSY Neaative True, Bus Currently BUSY

(Not !\vailable) Not Hsed

PE:O ~IeQative True, Request (RuS Data

Currently Valid) Not Used

--~---~--- ---

---

1325C:;

+2K Memory Module

13255-C)1064/07 Rev AUG-Ot-76

3.0 FUNCTIONAL nESCRIPTION. Pefer to the block diagram (figure 1),

sch~mattc diagram (fiqure 2), timinq diaqrams (figures 3, 4, and 5), component location diagram (tlgur~ 6), and parts list (02640-60064)

located in the appendix.

3.1

3.1 • t

3.?

3.? .1

3.1..2

The.+2K Memory Module consists of 2K of RAM, an address comparator, timinq and control loqic, multinlexinq logic, refresh logic, and bus

reque~t loqic circuits.

The memory portion of the PCA is comprised of four LST ^FA~ Chips, each oroanized 4K bv 1-bit. The chips are arranqed into an array of 4K hy 4. The 2K hy B-bit organization of the peA is achieved by making two read or write cycles per memory request. The RAM ch1ps have TTl,- comnatlhle inputs and outputs (except for CE CLnCK).

A read operation on the memory array requires that internal signal

~/W be high and that a1] ~ddress inouts be stable when CF CLorK (Chip Enable Clock) is asserted (ground to +12 volts). Internal signal Data Out (OU), is then routed to the two rearl reqisters (U15 and U16 in the ffiultlolexinq loqic), which store data from the two 4-bit read opera- tions. (Refer to figure ~ for read tlmlnq explanations.)

A write Is the sa~e as a memory read, except that R/W is held low.

DAta Tn (n1) comes from the input multiplex~r (TJ24) durlnq two 4-bit write operations. (Ret~r to fiaure 4 for write timing explanations.)

AnOQ£SS COMPARATOR.

The arldress comparator loqic is comnrised of a comparator (1138 ann 1139) and an address configuration 1umper nptwork (Wl). The 1umpers are used

to specity which 2K partition in the 64K memory space the t2K Memorv prA will represent.

The terminal bus PTovidPs 1~ address inouts (ADORO throuqh AODR15) and two control bits (I/U and WRIT~) which define module addressing.

13255

+2K Memorv Module 13255-91064/08

Rev AUG-01-7b

The most siqnificant five bits (AnD~15, AOOR14, ADOR13, ADDR12, and AOuPl1) are rout en to tpe address comodrator to determine if the memory peA is confiqt]red for the selected address. The remalnina 11 andress bits 00 to the memory chins throuqh inv~rters (U31 and (32) to preserve

t~rminal hus lo~dina rules. Other bus control inputs determine if a

m~morv operation is requested and distinguish whether it is a r~ad or write oneration.

3.2.'.1 The m@morv module uses the WRTT~ sianal to determine read or write access and uses I/O to inhibit a memory access durinq input/output operations. Another control incut, RFO, Is used ~nd is eauivalent to an execllte siqnal, which starts the memory access cycle.

3.2.2.? the final address bit to the memory chips, LSR ADDRESS (U213, Pin 9), determines which half of the 8-hit character is beinq accessen. When

3.3.1

3.3.2

the address comparator looic ^indi~ates an equal condition and I/O is hiqh, Module Accessed (1l3t1, Pin 6) is high as soon as REO gOPS low.

TTMING AND rUNTROL LO~Ir.

The tim!no an~ control loaic Is an interf~ce between the terminal bus and the memor1es. The control 10~ic nortion Of the peA accepts addr~ss

comnare (AOOR =1 information and hus control Innuts to determine If the module 1s b~lng acc~ssed. If it is, this block generates all timing and control signals necessary to access the memory Chips and perform the multiolexinq operation.

When the address comparator determines that the +2K Memorv peA is selected for a MOdule Accessed, the state counter (U211) beqins a

sequence Which aenerates the timing for two memory chip read or writes and the slqnals to control the multiplexinq. (Refer to figUres 3 and 4 for tYpical read and write cycle timing information.) The refresh logic alsO uses this block to perform pseudO read cycles.

132t)1)

+2K Memory Module

13255-91064/09 Rev AUG-01-76

3.3.2.1 The state counter (lJ211) Is a presetablp hinary counter which Is In the respt conriition until a mpmorv cycle is started by RlO and Module Splect beinq true. Two accesses to the 4~ by 4 array require a count, a pr.eset, an additional count, and a hold sequence (States 0, 1, 2, 7, 8, 9, and 10). Each count state represents about 203 nanoseconds (from SYS eLK of 4.Q15 ~HZ) and the states of the counter are decoded to derive the necessary control signals.

3.3.2.2 The timlnq and control loaic outputs qO to the chip clock driver (U23) and to the state counter to control its sequencing. The J,SB Address flip-flop is controlled bv the state counter: it is false durlna the first half of a memory module access and true on the second half. The read TPaisters (U15 and U16) receive LSB eLK (U311, Pin 11) and MSB

3.4

3.4.1

3.4.2

eLK (fT17, Pin 6) sinnals which clock Dl into them durinq read opera-

t~ons. Two other siqnals are generated bV the timinq and control loqic: R/W

-

(U27, Pin R) tells the memory to read or write and R~An

(U311, Pin R) enables the outputs of the read registers to be gated to the terminal bus during a mpmorv read. While the memOrY cycle is in proaress, WAIT Is held true (low). When the cycle is completed, WAIT

qoe~ false (high) and the state counter is halted (State 10). When RFO Qoes false (hiqh), the 2K ~emorv peA Is then ready for another mem- ory request.

MULTIP[,FXING LOGIC.

The multiDlexlnq loaic consists of an 8-to-4 multiplexer ch1p (U24) and two read reqisters (uts and U16). The outputs of the registers are connected to the terminal bus throuqh bus drivers, U25 and U26.

When a write cycle is initiated, data and address on the data bus are stable and the multiplexer gates the least Significant four bits (SUSO, BUS1, BUS2, and BUS3) to OJ in the memory chips. When the first memory write operation 1s complete, the LSR Address flip-flop changes and the most s!Qnlflcant four bits (BUS4 through BUS7) are gated to the chips.

This puts the least significant fOUT bits in even locations In memory and the most significant bits 1n odd locations.

13255

+2K Memory MOdule 13255·Ql064/tO

Pev .AUG-Ot-16

~.5

~hen a read access is oerformed, the data bus bits out Of the memory are strobpd into two 4-bit reao registers (1115 and UI6), with the least significant four bits (BIJ!;3, RlJS2, AUSt, and RUSO) heing strobed first.

Durino a read, the bus drivers (U25 and u26) are enabled and place the data in the read reaisters onto the terminal data bus.

RJ::FRESH LnGIC.

The refresh logic consists of a refresh address counter with bus drivers, ~nd portions of the timinq and control logic.

Dvn~mic ~ns memories require ~eriod1.c pseudo memory read cycles so that the intprnal data storaoe mechanisms do not lose data. A memory re- fresh cycle is initiated every 2 milliseconds and lasts approximately

4~.? ~icroseconds. All 64 refresh addresses are accessed in sequence, while the memory mOdule has contr~l of the terminal bus. (Refer to fiqure ~ for refresh cycle timing explanations.)

3.~.2 The refresh is ac~ompliSh~d bv ~erforminq 32 memory cycles Of two read operations. The least six siqnlfic~nt hits are cycled by qatinq the refresh address counter (five) hits onto the address bus and hack into the memOry chips and by toqqllna the I.SR address hit during pseudo read ("ycles.

3.5.2.1 The timing an~ control loaic is use~ to perforw the pseudO read cycles

t~ the me~ory Chips. At the pnd of e~Ch pseurlo rearl CYCle, the rpfresh address counter (U37) is incremented and the timinq and control loqic ooes to state 0 and beains a new read cycle.

1.5.2.7 When the ~ounter completes its count Of 32, the Refresh CYcle Complete flin-flop at H18, Pin 9 is set: the bus request loqic thpn releases the tprminal hus, and the refresh cycle ends.

3.6 RHS ~F.OlJES'l LOGTC.

3.6.1 The bus reauest loqic consists of four J-K flip-flops, gates anrl an astable (0112). The astable (U112) is used as a precision ti~er in the free run mode. The freauen~y is 500 Hz, qivinq a 2-ml111second refresh interval (5~O Hz +/-50 Hz).

1325~;

+2K Memory Module

13255-91064/11 Pev AUG-01-76

3.6.2 The astable clocks the first flip-flop siqnal RFFRESH R~QUEST, (utl0, Pin 6) ~nd a bUS request oppr~tlon is startpd. lhe second flip-floo

«(lIto, Pin B) buffers the RF"FPESH RF"QUEST siqnal and synchronizes it.

with the systprn clock. when the bus is available (RUSY is hiqh) and no other module is re~uestinq the tp.rminal bus, the 2K J~emory peA maKp.s BUSY low ~nd takes control of the terminal hus. An internal Bus Avail- able (aUS AVAIL) signal at UIQ, Pin 8 goes true, siqnalinq the start of the refresh cycle. The Bus Available signal qates the refresh counter (U37) outouts onto the terminal address bus.

ADDR1

,---,

2K MEMORY peA - - I

WAIT

WA!T

. ..

r

..

_I

..

^{READ EN}

.

I !

PRIOR IN _po

..

₂

- - I

--"' READ ClK 2

.. ..

WRITE

..

^O'

I

-1/0 --"'

..

TIMING ^AND RAM ENClK ...

..

^{4 DATA OUT}

..

8 READ DATA \.,.8 I . . .

I

I " ...

REO -"' CONTROL

DATA IN MULTI·

..

LOGIC READIWRITE ... 2K RAM .... 4 _PLEXING

-~ '" LOGIC L...8 WRITE DATA

SYS CLK

I

.

.. lSB/MSB SEL ... ~

r

I

^O'

••

r

..

,

PRIOR OUT

.. .. ..

ACS

.. .. ..

PRIOR OUT

REO

1-ADDR15 _I 5

r---.J ^ADDRESS COMPARATOR

I I

_ 5

~OA"'N'

^ADDRESS 4

, JUMPERS

ADDRO·

.... _'" ^{RFSH FN 5} PAD~

BUS BUS AVAIL. REFRESH

4 ^REOUEST

..

LOGIC

lOGIC

BUS AVAIL

" ^~

.4

l ______________________________________________ •

^I

⁺ __________________________ _

ADDRO·ADDR10

Flqure +2K MemorY AUG-01.-76

Rlocl< Diaqram 13255-91064

TO

BACKPLANf

r---~ - - - -

r--- - --- ---,

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Figure 2 ... 21\ Memory AUG-Ot-76

PCIt Schematic ~iagram

t3255-91064

j«Gr A:DOR. T1

WAIT

- - -

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CI! CLoCK

J.t10f)UI-E.; SEI-EC r

l-?l3 1'If)J)feJ;S$

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j...~B eLI< (STAT15 -7)

t1se Cl-I«(5TA"~!!J)

CONNECTote

&PINNO.

P/~PI/J ~

PI? PIN Y

PI.1 PIN 5 PI # PIN P

U 1/ Tf/£U U 14 ^J

PIN 17

U2 III

U.2.8, PIN 3

U2/~ .... PIN 3

U311 .. PIN B

U 3 11,PIN /I

U 17, PIN 6

/·2 A Sec. '-_ _ _ ...

,

~/~---~,

--

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+1'2.,.- - - ,

__________ ~:r_~S~H~~~.ONSOC-.I~ ____ ~)ff---

Q3-a_' _I 0000 10000: _I ^{000" 0010 : 0111} I/~oo: 1001: 1010 : /010 1/0/0 : 00(1) I

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Figure 3

+2K Memorv Read Timinq 01aqram AtlG-01-76 13255-91064

'SIGNAL NAMe

I;:E CI-Oc..1(

CONNEC10R

& PIN NO ..

PI, PIN ~

PI,PIN Y

PI,PIN P Ull TJ./eu u,~ PIN "

U311)PIN 8

r-

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+2K Memory Write Timing,Diaqram

AUG-01-76 13255-9t064

Ple/ote OUT

BUS AVAIL

GE CLOCK

~[;;FRcSH cyC/"c

COMPl.,t="Te

cONN£CrO/z"

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p,~ PIN 3

U 1/(4, PIN 8

PI~ PIN U

PI, PIN W U19~ PIN a

U211

U117HR.u U I,+:, PI J.J 17 U213, PI'" 9

U37 ANO U38

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Figure 5

+2K Mpmorv Pefresh Timing Diaqram

AUG-Ot-76 13255-91064

l1 _i m

02640-60064 MEMORY 2K A -1632- 22

Cl C2 C3

u GO

.- ^N M

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0 0

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Figure 0

+2K Mp.morv AUG"'Ol-7b. peA Co~ponent Location Diaqram 13255-91064

Reference Designation

C1

(;2 C3 v.

Cli) (;11 (,1.2

~B

C1,.

(,11.1

H E2 t:l fit

Kb tt7 Kci k9

Ul't>

Ul1 ul,t) U1';, Ul.L

U11,) U~'iI

UBO U.1 .. ~

Ul.LO UlU U2.L2

u~n

U3.L1

HP Part Number

02t40-,,006~

01!:0-01ll OBo-Ol21 01!:0-01ll OUo-01.21 Olt0-2055 Olt0-2055 OH0-2055 01 !:0-012l OUo-012l 01 !:0-0l21 Ol!:0-0121 OU0-20!>5 Oltu-2055

Olt0-220~

OH0-2055 OltO-Hlt3 OBo-012l Olt0-20,5 i>lt0-2055 OUo-174t.

OlfO-0393

o HO-O.2l93 01t0-2055 19C2-3u92 03to-0121t 03tO-0124 03to-0124 OltO-0124 06B-4715

01~1-01t42

0151-0200 06 U-'t71 5 06£3-10.25 06B-U05

06£3-~715

06t3-1U.25 1810-01.25 50E0-9785 50 to-9785 5ce0-97d5 50t0-9185 18£o-U95

UI~0-.1195 18~0-1l99

lCl£o-Ul2 18£0-1213 18£0-1l09

18~0-128a 18~o-lIt70

1820-1209 18£0-1209 18£0-1209

1~~0-1201 18~o-U97

184:o-U99

18~o-1l99 l8~0-1l9~

1820-l.215

18~o-1215 18~o-1213

18£b- 0373

UI£o-120~

1820-071b 1820-.1199 18£u-1112 1820-1l01

Qty

9

1 2

3 1 1 2

It

2

It 2 2

~

2 1

2

Replaceable Parts Description

~!~~R~~:~EMA~132~~

REVISION DATE: 08-04-76

CAPACITOR-fXD .1Uf +80-20~ 50.~DC CEa CAPACITOR-fXD .1Uf +80-20~ 5UW~OC Cfa CAPACITOR-fXD .1Uf +80-20~ 50.VOC CEa CAPACITOR-fXD .1Uf +80-20: 50wVDC CEg CAPACITOR-fXD .01Uf +80-20~ 100WVDC CER CAPACITOR-FXD .01Uf *8u-20~ 100WVDC CER

CAPACITCR-f~O .01Uf +80-20; 100WVDe CER CAPAC I TOR-f XC .1Uf +80-20; 50WVDC CEK CAPACITOR-fXO .1UF +80-20~ 50.VOC eER CAPACITOR-FXO .1Uf +80-20~ 50.VDC CER CAPACITOR-fXO .1UF +80-20' 50WVOC CEa CAPACITOR-fXO .01Uf +80-20~ 100WVOC CEa CAPACITOR-fXD .01Uf +80-20; 100WVOC CER CAPACITOR-fXD 100Pf +-5, 300~VOC MICA CAPACITOR-fXD .01Uf +80-20~ 100WVOC CER CAPACITOR-fXD .lUf+-l0~ 3~VDC TA CAPACITOR-fXD .1Uf +80-l0: 50.~DC CER CAPACITOR-fXD .01Uf +8o-20~ lOOWVDC CER CAPACITOR-fXD .01Uf ~80-20: LOO.VDe CER CAPACITOR-fXD 15Uf+-l0~ 20VDC TA CAPACITOR-fXD 39Uf+-l0~ 10VDC TA CAPACITOR-FXD 39Uf+-l0l lOVec TA CAPACITOR-fXD .01Uf +80-20: 100.VDC CER DIODE-ZNR ~.99V 2' 00-7 PD=.4W TC=-.012:

TERNINAl-STUD SG~-PIM PRESS-MTG TERMINAl-STUD SGl-PIN PRESS-MTG TERMINAL-STUD SGl-PIN PRESS-MTG TERMINAL-STUD SGl-PIh PRESS-MTG RESISTOR ~70 S' .2SW FC TC=-400/+600 RESISTOR 10~ l ' .125W F TC=0+-100 RESISTOR 5.62~ l ' .125~ f TC=0+-100 RESISTOR ~70 S' .25~ FC TC=-400/+600 RESISTOR lK 5~ .25. fC TC=-400/+600 RESISTOR 22 51 .25W FC TC=-1t00/+500 RESISTOR 470 5: .25W FC TC=-400/+600 RESISTOR lK 5~ .25W fC (C=-400/+600 NETWORK-RES 8-PIN-SIP .l25-PIN-SPCb 4K RAM 22-Plh HR

~K RAM 22-PI,N HR

~K RAM 22-PIN HR 4K RAM 22-PlN HR

IC-DIGITAl SN7~lS175N TTL lS QUAD JC-DIGITAl SN74lS175N TTL lS QUAD IC-DIGITAl S~7~lS04N TTL l~ HEX 1 IC-DIGITAl Sh74lS74N TTL lS DUAL IC-DIGITAl SN7~SI13M TTL lS DUAL IC-DIGITAl SN74lS38N TTL lS QUAD 2 HAND IC-DIGITAl MMH0026Cl TTl/MaS 1 CLOCK IC-DIGITAl SN7~lS151N TTL lS QUAD 2 IC-DIGITAl S~7~lS38N TTL lS QUAD 2 NAND IC-DIGITAl SN14lS38N TTL lS QUAD 2 NAND Ie-DIGITAL SN74lS38N TTL lS QUAD 2 NAND Ie-DIGITAL SN74lS08N TTL lS QUAD 2 AND IC-DIGITAl SN7~SOON TTL lS QUAD 2 NAND IC-DIGITAl SN1~lSO~N TTL lS HE~ 1 IC-DIGITAl SN7~S04N TTL lS HE~ 1 IC-DIGITAl SN7~lS193N TTL lS 8IN IC-DIGITAl SN7ltlS136M TTL lS QUAD 2 IC-DIGITAl SN74lS136M TTL lS QuAD 2 IC-DIGITAl SN74lS113N TTL lS DUAL IC -LINEAR

IC-DIGITAl SN7~S20N TTL lS DUAL It NAND IC-DIGITAl SN7~l6lN TTL SIN SYNCHRO IC-DIGITAl SN7~SO~N TTL lS HE~ 1 Ie-DIGITAL ~7~lSl~N TTL lS DUAL IC-DIGITAl SN7~S08N TTL lS QUAD 2 AND

Mfr Code

28480

28~8D 28~80

28480 28480 28480 281t80 28480 28480 28480 28480 28480

28~80

28480 28480 28480 56289 28480 28480

28~80

56289 56289 56289 28480 04713 28480

28~80

28480

28~80

01121 245't6

245~6

OU21 01121 01121 01121 01121 11236 28480 28480

28~80

28480 01295 01295 01295 01295 01295 01295 04713 01295 01295 01295 01295 01295 01295 01295 01295 01295 01295 01295 01295 01295 01295 01295 01295 01295

Mfr Part Number

02640-60064

0150-0121 0150-0121 0150-0121 0150-0121 0160-2055 0160-2055 0160-2055 0150-0121 0150-0121 0150-0121 01S0-0121 0160-20S5 0160-2055 0160-22a4 0160-2055 15001 04X9Ql S42 0150-0121 0160-2055 0160-2055 150D156X9020B2 150D396X9010B2 1500396X901082 0160-l055 SZ 10939-9t.

0360-0124 0360-0121t 0360-0124

0360-012~

C84715

CIt-1/8-To-1002-F CIt-1/8-T0-5621-f C84715

C81025 C82205 C84715 C81025 750 508.0-9785 5080-9785 508.0-9785 5080-9785 SN74lS175N

SN7~S115N

SN74lS0o\N SN74lS74N SN74lS113N SN7US38N MMH0026Cl

SN7~lS157N

SN-/4lS38N SN74lS38N SN761S38N

SN7~lS08N SN7~lSOON SN7~lSO~

SN14lS0~

SN74lS193N SN74lS116N SN74lS136N SN74lS113N

SN7~lS20N

SN7U61N

SN74lS0~

SN7~lS7o\N

SN14lS08N

Replaceable Parts Reference HP Part

Qty Description Mfr

Mfr Part Number

Designation Number Code

MEMORY ASSEMBLY. 2K CONT'D.

oil! J..<:eo-04d2 1 SOCKET-Ie l6-CONT DIP-SLO~ 91506 516-AG110

wlA 12!8-0124 5 PIN-PROGRA~MING JUMPER;.30 CONTACT 91506 8136-.75G1

wld 12!8-0124 PIN-PKOGRAH~lNG JUMPER;.30 CONTACT 91506 8136-415Gl

wi .. 12 !8-0124 PIN-PROG~AMMING JUMPER;.30 CONTACT 91506 8136-.1561

wlu 12 !d-0124 PIN-PR~RAMMING JUMPER;.30 CONTACT 91506 8136-,75Gl

11111: 12 !8-0124 PIN-PROGRAMMING JUMPER;.30 CONTACT 91506 8136-415G1