STM32: Peripherals
Emanuele Valea
valea@lirmm.fr
LIRMM - CNRS
November 28, 2019
STM32 System Architecture
STM32 System Architecture
S0: I-bus: This bus connects the Instruction bus of the Cortex-M4 core to the BusMatrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal Flash memory, the SRAM and the Core Cupled Memory (CCM) RAM.
S1: D-bus: This bus connects the DCode bus of the Cortex-M4 core to the BusMatrix. The targets of this bus are the internal Flash memory, the SRAM and the CCM RAM.
S2: S-bus: This bus connects the system bus of the Cortex-M4 core to the BusMatrix. This bus is used to access data located in the peripheral or SRAM area. The targets of this bus are the SRAM, the AHB to APB1/APB2 bridges, the AHB IO port and the ADC.
STM32 System Architecture
S3, S4: DMA-bus: This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of dierent Masters to Flash, SRAM and peripherals.
The DMA (Direct Memory Access) is a peripheral that transfer data between peripherals and memories without involving the CPU.
Memory map
Peripherals are memory mapped
Memory map
General purpose input/output
Memory map
Reset and clock control (RCC)
Memory map
External Interrupt
Memory map
The SRAM represents only a "tiny" part of the memory mapping!
Reset and clock control (RCC)
System clock (SYSCLK) selection (three dierent clock sources):
I HSI 8 MHZ RC oscillator clock I HSE oscillator clock
I PLL clock
RCC registers allow to enable the use of a particular peripheral I When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0.
RCC_AHBENR, RCC_APB1RSTR, RCC_APB2RSTR
Interrupts
Programs are executed sequentially (one instruction after the other). But a computer that can only execute a predened program is not very useful
I We need to introduce the possibility to interact with the external world
The interaction is obtained introducing the concept of interrupt
Interrupts are external (or internal) events that modify the execution ow of the program
Many examples that we use every day:
I Touchscreen I Keyboard
I Temperature control I ...
Interrupts
Interrupts are associated to special events
When these events occur, the CPU stops executing its main program and starts executing a specic Interrupt Service Routine (ISR) associated to the specic interrupt
When the ISR terminates its execution, the main program is resumed from where it was left
Interrupt Service Routines are quite similar to functions, but they also have big dierences:
I They are always associated to a specic interrupt. Each interrupt has its own ISR.
I They are executed only if the associated interrupt occurs.
I The addresses of all the ISRs are stored inside the Interrupt Vector Table
Interrupts
They can be synchronous or asynchronous:
I Synchronous interrupt: it is triggered by the software.
Example: illegal instruction, division by 0.
I Asynchronous interrupt: it is triggered by an external event.
For this reason, it can interrupt the execution of the code without waiting that the current instruction ends its execution.
Example: external reset, push-button.
They can be maskable or unmaskable:
I Maskable interrupts: they can be enabled/disabled by software.
I Unmaskable interrupts: they cannot be disabled by software.
Example: external reset, system failure.
Each interrupt has a priority level: if a high priority interrupt is triggered while the ISR of a low priority interrupt is being executed, this stops its execution and the higher priority ISR is executed.
Managing peripherals
Peripherals can be managed resorting to two strategies:
I Interrupt I Polling
In the interrupt approach the CPU waits for the peripheral to send an interrupt and notify that something happened
In the polling approach, the CPU continuously checks if something new happened on the peripheral (massive usage of loops)
Polling VS Interrupt
INTERRUPT POLLING
Basic Device notify CPU that it needs CPU attention.
CPU constantly checks device status whether it needs CPU's attention.
Mechanism An interrupt is a
hardware mechanism. Polling is a Protocol.
Servicing Interrupt handler
services the Device. CPU services the device.
Indication Interrupt-request line indicates that device
needs servicing.
Comand-ready bit indicates the device needs servicing.
CPU CPU is disturbed only when a device needs servicing,
which saves CPU cycles.
CPU has to wait and check whether a device needs servicing which
wastes lots of CPU cycles.
Occurrence An interrupt can
occur at any time. CPU polls the devices at regular interval.
Eciency
Interrupt becomes inecient when devices keep on interrupting the CPU
repeatedly.
Polling becomes inecient when CPU rarely nds a device ready for service.
Let the bell ring Constantly keep on opening
Example: Using user button on STM32 in polling
Example: Using user button on STM32 in polling
Once the button activated, the CPU has to verify periodically whether the button was pressed or not.
I Create a function which reads the state of the GPIO port input data register (GPIO_IDR)
I Invoke the function periodically
I if you nd a specic value, then it means that the button was pressed and a specic action can be performed (e.g., you can switch on/o a led)
Interrupts scheme
Interrupts
Nested vectored interrupt controller (NVIC) main features I 74 maskable interrupt channels
I A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority
I Low-latency exception and interrupt handling
The NVIC and the processor core interface are closely coupled I this enables low latency interrupt processing and ecient
processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC.
Interrupt Vector Table
EXTI
Extended interrupts and events controller (EXTI) Manages the external and internal asynchronous
events/interrupts and generates the event request to the CPU/Interrupt Controller and a wake-up request to the Power Manager.
An interrupt could be left pending;
I for external interrupts, a status register indicates the source of the interrupt;
I for internal interrupts, the pending status is assured by the generating peripheral, thus no need for a specic ag.
Each input line can be masked independently.
External and internal interrupt/event line mapping
36 interrupt/event lines are available: 8 lines are internal (including the reserved ones); the remaining 28 lines are external.
The GPIOs are connected to the 16 external interrupt/event lines in the following manner:
Conguring Interrupts
For the external interrupt lines the interrupt line should be congured and enabled.
I This is done by enabling the interrupt request by writing a "1"
to the corresponding bit in the interrupt mask register (IMR).
When the external interrupt line receives a signal, an interrupt request is generated and the corresponding pending bit is also set.
Conguring Interrupts
In practice, to congure a line as interrupt source, use the following procedure:
I Congure the system controller to manage the external interrupt line connection to the GPIOs
I Congure the corresponding mask bit in the EXTI_IMR register.
I Congure the Trigger Selection bits of the Interrupt line (EXTI_RTSR and EXTI_FTSR).
I Write the Interrupt Service Routine.
I Clear the pending request.
External and internal interrupt/event line mapping
External and internal interrupt/event line mapping
Enable SYSCFG clock
External and internal interrupt/event line mapping
Conguring Interrupts
Congure the corresponding mask bit in the EXTI_IMR register:
Conguring Interrupts
Congure the Rising Trigger Selection bits of the Interrupt line (EXTI_RTSR)
Conguring Interrupts
Congure the Falling Trigger Selection bits of the Interrupt line (EXTI_FTSR)
Conguring Interrupts
Write the Interrupt Service Routine (Vector Table)
Conguring Interrupts
Congure the NVIC Interrupt set enable register (NVIC_ISER) to activate the interrupt
This will "wake up" (interrupt) the processor, asking it to serve the request
Conguring Interrupts
Find the Name of the Interrupt service routine (ISR)
Write your ISR with the same name to perform an action.
Conguring Interrupts
Clear the pending request.
