Development of inkjet-printed inverters

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https://doi.org/10.4224/23000711

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Development of inkjet-printed inverters

Chu, Ta-Ya; Dadvand, Afshin; Graddage, Neil; Py, Christophe; Lang, Stephen; Tao, Ye

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Ta-Ya Chu, Afshin Dadvand, Neil Graddage, Christophe Py, Stephen Lang,

and Ye Tao

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Outline

• Introduction

• Development of 3-layer-printed OTFTs

• Different types of printed inverter developed at NRC

 Enhancement-load PMOS inverter

 PMOS inverter (screen printed resistor)

 CMOS inverter

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Challenges in printing process

Challenges  yield, stability

 Uniformity, Roughness  Interface interaction  Solvents compatibility  Drying process  Printing platform Printing process Thermal evaporation Spin coating 1985 1990 1995 2000 2005 2010 2015 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200

Organic light emitting Organic transistor Printed transistor N u mb e r o f p u b lica ti o n Year

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Polymer based transistor backplane is required for

flexible/bendable electronics in the future

Polyera smartwatch using OTFTs Flexible Curved Foldable Bendable

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NRC 3-Layer-Printed Organic Thin Film Transistors (OTFTs)

 No spin coating process

 Printing process in ambient air

3-layer-printed OTFTs Ag Dielectric S D PET Substrate Organic Semiconductor

Inkjet printed layers

 Organic semiconductor  Dielectric

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-300 -200 -100 0 100 200 300 -50 0 50 100 150 200 250 300 350 400 450 500 550 600 He ig ht [nm] Width [m] 1 Nozzle 2 Nozzles 3 Nozzles

Thin and uniform printed dielectric layer enabled by the

coffee ring effect

-60 -40 -20 0 20 40 60 0 200 400 600 800 1000 Drop Spacing 15m 25m 35m 45m 55m He ig ht [nm] Width [m] Organic Electronics 29 (2016) 114-119

 Transistor driving voltage is proportional to the thickness of dielectric layer

 Difficult to achieve a pin-hole free of thin dielectric layer by printing method

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3-layer-printed OTFTs mobility up to ~1 cm

2

_{/Vs at 15 V}

0 2 4 6 8 10 12 14 16 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 (-I DS ) 1 /2 ( 1 0 -3 A 1 /2 ) -V_G (V) -IDS ( A ) =1.0 cm2/Vs V_DS=-15 V 0 2 4 6 8 10 0 2 4 6 8 10 12 14 16 18 20 0 10 20 30 40 50 60 70 -IDS (  A) V_DS (V) V_GS (V) -1 -3 -5 -7 -9 -11 -13 -15

Channel length 5 µm, channel width 1 mm

Dielectric thickness~ 250 nm Max. Processing Temp. 140°C

0.2 0.4 0.6 0.8 1.0 1.2 1.4

420 OFETs (8 OFETs, 2%, mobility lower than 0.2 cm2/Vs are not counted for statistics)

Mob ility (cm 2 /V s) 0.86 Standard deviation 0.15 (17%) 3-layer-printed OTFTs Ag Dielectric S D PET Substrate DPP-DTT

Average mobility of 0.86 cm2_{/Vs (variation}σ~15%) with

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-0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 Input_Output Vo lt a g e (V) Time (sec) Vdd=-20V, 100 Hz

Printed PMOS enhancement-load Inverter and relative

logic circuits

Vout Vin Vdd Channel length L= 5 µm, Channel width  Drive transistor W=1 mm  Load transistor W=200 µm,

Simplest printing process and excellent stability Lower output amplitude

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Printed logic gates NAND, AND, NOR and OR

Table 1. Truth tables for NAND, AND, NOR and OR logic gates Output for the different logic gates

Vin 1 Vin 2 NAND AND NOR OR

1 1 0 1 0 1

1 0 1 0 0 1

0 1 1 0 0 1

0 0 1 0 1 0

NAND NOR AND OR

Vdd=-30V -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 -20 -10 0 -20 -10 0 -20 -10 0 -20 -10 0 -20 -10 0 -20 -10 0 Time (sec) OR NOR AND NAND Vin2 Volt age (V) Vin1

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Printed PMOS inverter using screen printed resistor

0 1 2 3 4 5 0.5 1.0 1.5 2.0 2.5 3.0 D e la y t im e ( m s )

Resistance of the external resistor (M)

Vout Vin Vdd -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 -16 -14 -12 -10 -8 -6 -4 -2 0 2 Vo lt a g e (V) Time (sec)

Printed inverter (Inkjet printed OFET/ Screen printed resistor) Input

Output

OFET (L=5m, W=1mm), Screen printed resistor

Screen printed carbon ink for resistor

-14 -12 -10 -8 -6 -4 -2 0 -16 -14 -12 -10 -8 -6 -4 -2 0 V_in (V) V out (V ) 0 1 2 3 4 5 6 7 8 9 10 G ai n

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0 5 10 15 20 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 S Q R T I D S (m A ) Lo g I D S (A ) V_GS(V) v_DS=20 0 5 10 15 20 0 2 4 6 8 10 12 0 V 4 V 8 V 12 V 16 V 20 V IDS (  ) V_DS(V)

3-Layer-Printed

N type transistor

Organic Electronics 29 (2016) 114-119 Dielect. Thick. (nm) Mobility (cm2_/Vs) @ bias=20 V V_th (V) On-current (A) Off-current (A) On/Off

800 0.01 12.8 2.5E-07 1.16E-12 2.1E+05

450 0.05 10.9 3.2E-07 1.20E-12 2.6E+05

300 0.05 9.7 5.0E-07 7.15E-12 7.0E+05

220 0.10 8.4 8.8E-06 6.24E-11 1.4E+05

180 0.12 4.1 1.5E-05 6.70E-10 4.0E+04

Development of printed CMOS inverter

NDI2OD-T2 N-type semiconductor 3-layer-printed OTFTs Ag SOG Dielectric S D PET Substrate

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Ag Ag Dielectric Dielectric N P Vdd Vout Ground PET Substrate DPP-DTT

P-type semiconductor _{N-type semiconductor}NDI2OD-T2

V

in

V

out

V

dd

P

_N

Development of printed CMOS inverter

Difficulties

 Compatible processing condition for both P and N type materials

 Compatible IV characteristics  Stability between P and N

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25 20 15 10 5 0 0 3 6 9 12 15 18 21 24 0 3 6 9 12 15 18 21 24 10 V 15 V 20 V 25 V V ds (V ) V gs(V) Gain 0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 12 14 16 18 20 Vo u t Time (sec) Output Input

Development of printed CMOS inverter

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 2 4 6 8 10 12 14 16 18 20 O u tp u t (V) Time (sec)

Printed CMOS driven at 10Hz (15V, exposed in air) Initial

1 hr 2 hrs 7 hrs 80 hrs

 Full-swing output amplitude achieved  Gain value of 24 obtained

 Air stability testing without encapsulation

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Summary

 NRC developed printing process for 3-layer-printed OFETs, mobility of 1 cm2_{/Vs on}

PMOS and 0.1 cm2_{/Vs on NMOS transistors have been achieved.}

 Introduced coffee ring effect to achieve thin and uniform dielectric layer by inkjet printing process.

 Gain value of 24 with a nearly full-swing of output voltage obtained from the printed CMOS inverter.

 Demonstrated the air stable printed CMOS without encapsulation

Summary

Printed circuits

Semiconductor

Electrode Dielectric

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Thank you for your attention!

Question?

Dr. Ta-Ya Chu Research Officer Tel: 1-613-949-7558 ta-ya.chu@nrc-cnrc.gc.ca www.nrc-cnrc.gc.ca

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