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A 9GHz injection locked loop optical clock receiver in 32-nm CMOS

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Academic year: 2021

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Figure

Figure  1-1:  An intra-chip  integrated  photonic  link  implementing WDM.  An inter-chip link  may be  implemented  similarly
Figure  2-1:  Cross-section  and  SEM  image  of  the  waveguides  and  air  gap.  Note  that the  air  gap  does  not  reach  the  transistors
Figure  2-2:  Illustration  of  ring  modulator.  Note  that  diodes  were  only  implemented on  the straight  sections  of  the ring  due  to fabrication  constraints
Figure  3-1:  Conventional  source-synchronous  unidirectional  and  differential  point-to- point-to-point  parallel  link,  where  the  clock  is  sent  along  with  data  for  easy  receiver  timing recovery
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