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JFET FOR COMPLETELY DEPLETED HIGH RESISTIVITY SILICON
V. Radeka, P. Rehak, S. Rescia, E. Gatti, A. Longoni, M. Sampietro, G.
Bertuccio, P. Holl, L. Struder, J. Kemmer
To cite this version:
V. Radeka, P. Rehak, S. Rescia, E. Gatti, A. Longoni, et al.. JFET FOR COMPLETELY DEPLETED HIGH RESISTIVITY SILICON. Journal de Physique Colloques, 1988, 49 (C4), pp.C4-363-C4-366.
�10.1051/jphyscol:1988475�. �jpa-00227973�
JOURNAL DE PHYSIQUE
Colloque C4, suppldment au n 0 9 , Tome 49, septembre 1988
JFET FOR COMPLETELY DEPLETED HIGH RESISTIVITY SILICON
V. RADEKA, P. REHAK, S. RESCIA, E. GATTI*, A. LONGONI*, M. SAMPIETRO*, G. BERTUCCIO*, P. HOLL**, L. STRUDER** and J. K E M M E R * ~ "
Brookhaven Nat. Lab., Upton, NY 11973, U.S.A.
" ~ o l i t e c n i c o di Milano, Dipartimento di Elettronica e Centro di Elettronica Quantistica e Strumentazione Elettronica CNR, P.za Leonardo da Vinci 32, I-20133 Milano, Italy
* * Max-Planck-Institut, Fohringer Ring 6 , 0-8000 Miinchen, F.R.G.
**'Tu Miinchen, 8048 Garching and MBB GmbH, Postfach 801149, 0-8000 Miinchen 80, F.R.G.
Resume
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On presente le projet d'une nouvelle classe de transistors a effet de champa
jonction JFETs, consue pour I'integration sur le wafer a haute resistivite d'un detecteur de radiation completement en depletion, et les resultats experimenteaux obtenus. Ces dispositifs vont rendre possible I'integration d'un preamplificateur B faible bruit directement sur le detecteur et par consequent une amelioration de la resolution. Ces nouveaux JFETs ont ete projetes pour obtenir un g m / C ~ de 500 MHz et on a mesure pour eux un g m / I ~ de 11850 mv-I et un pinch-off de 1.5 V.Abstract
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The design and the experimental results of a new class of JFETs, suitable for integration on the high resistivity wafer of a fully depleted radiation detector, are presented.These devices will make possible the integration of a low noise preamplifier directly on the detector, improving the achievable resolution. The new JFET has a measured g m / I ~ of 11850 m v - l , a pinch-off of 1.5V and a designed g m / C ~ of 500 MHz.
1 - INTRODUCTION
During the last few years, there has been an increasing interest in the integration of front end electronic circuits onto some new type of fully depleted large area detectors for position and energy measurements of ionizing radiation (Semiconductor Drift Chambers, fully depleted CCD, etc.) /1,4/.
As it is well known, the signal-to-noise ratio for amplitude measurements, as well as the timing resolution, increases by lowering the output capacitance of the detector and matching to this capacitance (which includes stray capacitances of connection to the preamplifier) the capacitance of the input device of the preamplifier /5,6/.
These detectors can be built with a very low output capacitance of the order of tens of femtofarad practically independent of their active area /7,9/.
The energy and position resolution achievable with these detectors have been limited, so far, by the excessively high input capacitance of even the best commercially available descrete field effect transistor.
To fully exploit the unique property of very small capacitance of these detectors, it is compulsory to build the input preamplifier on the same chip of the detector. In this way it is possible to reduce to negligible values the strays of the connections and to design an input FET with a capacitance matched to the detector one.
2
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DESIGN SPECIFICATIONS OF THE INTEGRATED JFETThe peculiar characteristics of the detectors impose some design constraints to integrated JFETs /lo/ :
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Implementation on the detector wafer (high resistivity, detector grade, n-type silicon, ZKohm.cm,<11 I> surface orientation).
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Implementation with the limited production steps used for the detector. In effect in order to' keep the leakage current low, only relatively low temperature (800 C) processes in the detector production are allowed, with no diffusions and no polysilicon process presently available.
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requirement of operation on a fully depleted n-type substrate.-
surface connection of the p+ gate with the n+ output anode of the detector.Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988475
JOURNAL
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PHYSIQUE3
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STRUCTURE O F THE JFETA schematic cross section of the device is shown in Fig.1. The doping is obtained exclusively by ion implantation. The Source and Drain electrodes are obtained with a high dose, low energy Phosphorous implant ( 5 ~ 1 0 ~ ~ c r n - ~ , :)OkeV), while the Gate is obtained with a high dose, low energy Boron implant ( 5 ~ 1 0 l ~ c m - ~ . , 12.5keV). A deep Phosphorous implant ( 8 . 5 ~ 1 0 ~ l c m - ~ , 520keV), centered at 0.65 um depth in the bulk, forms the channel of the FET. A deeper Boron implant ( 1 . 8 ~ 1 0 ~ ~ c m - ~ , 480keV), centered at 1.03um depth in the silicon bulk, separates the n+ channel from the underlying completely depleted bulk.
3 i
,,,,,JJ
V)
I Back cantact (pc)
Fig.1
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Schematic cross section of the JFET built on high resistivity silicon.The fixed negative charges of the depleted Boron deep implant create an electric field which enhances the confinement of the electrons injected from the source within the n+ channel. Fig.2a shows the effectiveness of the deep p+ implant in confining the electrons in the channel. Curve A represents the case in which the deep p+ implant is present, curve B the one in which the deep p+ implant has been omitted. A schematic 3D plot of the electron potential energy in the Source and Gate region of the transistor is shown in Fig.2b.
In order to isolate each transistor from the others in the integrated amplifying circuit and from the detector sensitive area, the device is surrounded by a thin p+ electrode reverse biased with respect to any present n+ electrode. The bulk is completely depleted of all mobile charges by a suitable high negative bias voltage at the p+ implant on the back side of the wafer. Silicon nitride has been deposited for passivation purposes and to allow the deposition of the required aluminium connections.
Fig.2 -a) Potential in the channel region with (curve A) and without (curve B) deep p+ implant.
Only 30um depth is shown. b) Schematic 3D plot of the potential energy for electrons in the Source and Gate region of the JFET, with a negative bias applied to the Gate and OV to the Drain.
The described structure has been used for JFETs of different geometries. Some of the geometrical parameters are the same f o r nearly all the transistors designed, in particular the Gate length is 7um, the spacing between the Gate implant and the Source and Drain implants are respectively 4um and 5um. The Gate width ranges between lOOum and 2000um. Small transistors have a central square Source completely surrounded by concentric gate and Drain electrodes. Larger transistors have a comb structure.
A test wafer with JFETs of different geometries has been produced. Each transistor has , as mentioned in section 2, an n+ pad connected to the gate simulating the anode of the detector and used as a connection pad for bonding and testing, and n+ source and drain pads of suitable dimensions f o i a wedge bonding, all electrically insulated by p+ guards. Some n+ additional pads have been integrated near the transistor in order to collect the reverse current from the depleted bulk.
4 - CHARACTERIZATION O F THE JFET
All the produced test transistors have been successfully tested. The ID-VDS characteristics of a transistor having a gate width of 100 urn are shown in Fig.3a and the corresponding transcharacteristic ID-VGS for VDs=2.5V is shown in Fig.3b.
a p p r o x i m a t i o n
e x p e r i m e n t a l
1
0.0 . 4 . 8 1.2 1.6 2.0
-Vgate C V I
Fig.3 - a) Characteristics of the JFET (Hor. O.SV/div., Vert. 5OuA/div, Vgate 2OOmV/step).
Vback=-140V, \rguard=-3.5V. b) Related transcharacteristic curve for V D S = ~ . ~ V
The resulting pinch-off voltage is V =-1.5V. The maximum transconductance gm, at Id=260 uA, is 0.3 mA/V corresponding to a gm/ID=1/850 m 8 - I . The gate capacitance CG is extimated to be of the order of 0.1 pF, and therefore the value of g m / C ~ is expected to be of the order of 500 MHz. The slope of the ID-VDS curve in the saturation region corresponds to an output resistence of 50 kOhm.
Note in Fig.3b that the square law approximation of the transcharacteristic fits very well. the experimental points. This is due to the fact that this relationship is obtained for the simplified configuration of a delta charge distribution in the channel , which represents quite well the deep n+
implantation of the described JFET.
Note that the measurements shown in Fig.3a and 3b were performed with n+ contacts in proximity of the JFET connected to ground. These contacts collect most of the current from the depleted bulk and from the reverse biased p+ junctions, which otherwise would be collected by the Drain, giving a non neglegible Id current in pinch-off conditions.
The Gate current is the algebraic sum of different components, as shown graphically in Fig.4a:
11 - bulk current (electrons collected by the n+ Gate pad),
I2 - reverse current of the junction formed by the p+ Gate electrode and the n+ channel (electrons emitted by the p+ Gate electrode),
I3 - reverse current of the junction formed by the n+ Gate pad and the surrounding p+ guard (electrons collected by the n+ Gate pad),
14 - current exchanged between the n+ Gate pad and the n+ Drain and Source electrodes and pads (electrons emitted by the n+ Gate pad).
Fig.4b shows the measurement of the Gate current as a function of the Gate to Source voltage of the JFET connected as a diode with the Drain short circuited to the Source. Curve A shows the case with external n+ contacts connected to ground and p+ guards reverse biased with respect to the Gate. Curve B shows the case with p+ guards connected to ground. Curve A shows that in operating conditions for the JFET ( V D G < ~ V ) the Gate current is less than one tenth of a nA. Curve B is presented in order to show,
C4-366 JOURNAL
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PHYSIQUEGate pad Gate
Fl
ExternalPI 6 1
01 1E-09
0
...
&
1E-I0....?... '.
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1E-11...
curve A1E-12
IE-13
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,, 1
0 2 4 6 8 10
Fig.4
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a) Scheme of the different current contributions to Igate to show their signs and origins. Arrows and signs are shown according the usual convention.b) Gate currents of a diode-connected FET (D and S short-circuited) as a function of VDG under different guard biases: curve A VgUard=-2V, curve B VgUard=OV. Guard potentials referred to the Gate.
i n comparison with curve A, the effectiveness of a negative bias (with respect to the Gate) applied to the guard i n screening the Gate n+ pad from collecting the bulk current 11 and i n blocking the 14 component. In the case of curve B, approximatively I uA of current is collected by the n+ Gate pad, while in the case of curve A most of this current flows to the external n+ pads and only the I2 and I3 components (approximately one tenth of a nA) flow to the Gate pad.
In case of curve A, the Gate current is dominated by I1 for V D G < ~ V ( VDG<7.5V for curve B), while for higher VDG it is dominated by 14. These two components have opposite sign and the prevailing of one over the second determines the change in sign of the overall Gate current shown in Fig.4b. The components I2 and I3 are neglegible in the polarization conditions presented. The low value of the total gate current is surely not due to a compensation effect of much larger currents of opposite signs because of its relatively slow variation in a relatively large range of bias conditions. Such a low value of the gate current much less than the reverse current of the detector, will make its shot noise contribution negligible with respect to the one associated with the detector leakage current.
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CONCLUSIONSIn view of the integration of a low noise preamplifier on the high resistivity fully depleted silicon wafer of a radiation detector, the required JFETs have been produced and tested. Due to the operational and technological constraints posed by the detector, a new non conventional design of the transistors has been introduced. The measured performances of these JFETs meet the the design specification and show the possibility of an improved low noise processing of the detector signal.
Research supported by the U.S. Department of Energy (Contract No. DE-AC02-76CH00016) and by the Italian INFN and CNR, Progetto Finalizzato MADESS.
REFERENCES
/ I / E.Gatti, A.Longoni, M.Sampietro, 17 European Solid State Device Research Conference
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ESSDERC 1987, Proceedings pg.9/2/ J.Kemmer, Nucl.Instr. and Meth. A253 (1987) 365 /3/ V.Radeka, Nucl.Instr. and Meth. 226 (1984) 209
/4/ L.Struder, P.Holl, G.Lutz and J.Kemmer, Nucl.Instr. and Meth. A253 (1987) 386 /5/ E.Gatti,P.F.Manfredi, Riv. Nuovo Cimento 9, n.1 (1986)
/6/ V.Radeka, Nucl.Instr. and Meth. A253 (1987) 309 /7/ E.Gatti, P.Rehak, Nucl.Instr. and Meth. 225 (1984) 608 /8/ E.Gatti e t al., Nucl.Instr. and Meth. 235 (1985) 224 /9/ P.Rehak et al., Nucl.[nstr. and Meth. A248 (1986) 367 / l o / V.Radeka et al., IEEE Trans. Nucl. Sci. Vol.NS35-n.1-Feb.88
