Power supply constraints in megabit DRAMs of the future

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Power supply constraints in megabit DRAMs of the future

K. Itoh, K. Kimura

To cite this version:

K. Itoh, K. Kimura. Power supply constraints in megabit DRAMs of the future. Re- vue de Physique Appliquée, Société française de physique / EDP, 1987, 22 (1), pp.15-19.

�10.1051/rphysap:0198700220101500�. �jpa-00245508�

Power supply constraints in megabit DRAMs of the future

K. Itoh and K. Kimura

Central Research

Lab.,

^Hitachi Ltd,

Kokubunji, Tokyo

^185,

Japan

(Reçu

^{le 28}

juin

1985,

accepté

^{le 9}

juin 1986)

Résumé. ²⁰¹⁴ La densité des mémoires DRAM a été

multipliée

par quatre ^{tous les trois ans. Le}

développement

^des

mémoires 1 Mb est d’ores et

déjà

très avancé. L’évolution de l’alimentation est donc

d’importance capitale

^étant

donné les réductions des dimensions

qui

^sont intervenues.

Abstract. ²⁰¹⁴

Megabit

^DRAM power

supply

is described in terms of power

dissipation, reliability

^{for small} transistors, and memory cell

operating margin.

^Such

recently developed

^{1 Mb}

techniques

^{as CMOS and}

vertically

^structured

memory cells ^are discussed. It is concluded that, in

spite

^{of CMOS}

advantage,

^a transition from the

existing supply voltage

^{of 5 V}

might

^{occur at} the 16 Mb level.

Classification

Physics

^Abstracts

85.40

1. Introduction.

The

density

^of

dynamic

random-access memories

(DRAMs)

^has

quadrupled

every three years. ^{In line} with

this,

^the

development

^{of 1 Mb DRAMs}

[1-12]

^as

the next

step

^{from the}

existing

^{256 kb is}

already

^under

way. This

rapid

^{evolution in DRAMs has been realized}

mainly by

^the progress ⁱⁿ

photolithography

^{and one-}

device cell. Such progress has made it clear that one of the

major

^{concems in the}

megabit

^DRAMs

design

ⁱⁿ

the near

future

^{is the} issue of _power

supply voltage.

This issue is considered in this _paper.

First,

^{it is shown} how the

supply voltage

^is

closely

^{related to} power

dissipation

^and submicrometer transistor character-

istics,

which constrain the upper limit of the

supply voltage. Next,

^a one-device cell

operating margin,

which constrains the lower limit of the

supply voltage,

is

discussed,

^followed

by

future considerations concem-

ing

the power

supply.

2. Power

dissipation.

There is a definite trend of increased _power

dissipation

with

increasing

^bit

density

^{for a}

given supply voltage, V cc’

^{as shown in}

figures

^{1 and 2. This is due to}

increases in both

peripheral

current,

ip,

^{and in memory}

array current,

i A,

^{as shown in}

figures

^{3 and 4. It should}

be noted that the contribution of

i A

^{to the total} power

dissipation

^{becomes more and more}

pronounced

^{as the}

bit

density increases.

^{The increase in}

ip

is caused

by

increased load

capacitance

ⁱⁿ

peripheral

circuits due to

an increase in the number of decoders and an increase in

chip

^{size of about 1.5} times for _every successive

REVUE DE PHYSIQUE APPLIQUÉE.-T. 22, N’ 1, JANVIER 1987

Fig.

^{1. - Trends in}

supply voltage

and power

dissipation.

Fig.

^{2. - Power}

dissipation analysis

for NMOS DRAMs.

2

Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/rphysap:0198700220101500

16

Fig.

^{3. - Factors}

constraining

^the

supply voltage

^{in Mb}

DRAMs.

Fig.

^{4. -}

Logical

DRAM memory array

configuration.

generation

^DRAM

[13].

The increase in

i A

^{is due to the}

increase in total data line

capacitance, mnCD.

^{In order}

to offset these

capacitance increases,

power reduction

techniques

^{have been}

employed

^{in each}

generation

DRAM : 16

K ; j8

^{was reduced}

by

^{half due to a}

doubling

^{of n. In}

addition, dynamic

^sense

amplifiers [14]

^was

introduced,

⁶⁴

K ;

power

dissipation [15]

^was

drastically

^reduced

compared

^{to the}

previous

gener-

ation, by reducing

^the

supply voltage

^{from 12 V to 5 V}

while

maintaining

^{the same}

tREF max/n,

²⁵⁶

K ; tREF

max was doubled while

j8

remained the same

[16].

However,

^{this has not been the case with the 1 Mb}

generation. Reducing

^the

supply voltage

^{to 3.3 V was}

proposed

^{in the}

early stage

^{of 1 Mb}

development

^to

reduce power

dissipation

^{and to insure}

high reliability

in small transistors.

Eventually,

^a

Vcc

^{of 5 V was}

chosen as a result of the

following

low power

techniques

combined with a further increase in

tREF

^{max : the use}

of CMOS

[3-7]

instead of the traditional

NMOS,

^the

use of ^a half

Vcc precharge

^{on the data lines}

[2, 4-9],

the use of an

on-chip voltage

limiter circuit

[1, 3]

^and

the use of multidivision data lines

[1, 4, 9].

It was not until the 1 Mb

generation

of DRAMs that CMOS DRAMs

[17-19]

^were

seriously

taken into consideration. This is

because,

^as

long

^{as NMOS is}

used,

^{it is too difficult to}

design

^a low power 1 Mb

chip

in

spite

^{of a refresh}

cycle,

^{n, which has increased from}

256 to

512,

^{as shown in}

figure

^{2. The use of CMOS}

clock drivers and decoders in

peripheral

circuits dramat-

ically

^reduces

i p by

^{about half.}

Furthermore,

^{the use of} CMOS

permits

^the

implementation

of low power

special

^{functions such as a} static column mode. The data line

precharged voltage, Vp,

^can be reduced

by

half

using

^{a half}

Vcc precharge. This,

ⁱⁿ turn, ^{results in}

a reduction of the array current,

i A,

^as shown in the

equation

ⁱⁿ

figure

^{3. This}

approach

is desirable for

application

^{in CMOS because it} facilitates an area-

saving layout

^{as well as offers a wide}

operating margin

for

amplifiers

^{and active restore} circuits. Another way to reduce

Vp

has also been

proposed :

memory array

operation

should be based on a reduced

voltage, generated by

^an

on-chip

^limiter while the

voltage supplied externally

^is maintained at 5 V.

ip

^{can also be}

reduced very

effectively by reducing CD.

^{This can be}

accomplished by using

^a multi-divided data line struc- ture. This reduction in

CD

also results in an increased memory cell

signal voltage.

^{Such a data line structure,}

using

^{two-level aluminum}

wiring,

^{has been}

reported

^to

reduce

by

^{2/3 the data line}

capacitance

^{for a}

given chip

area.

Despite

^these

past attempts

^{to achieve} low power

dissipation

^while

maintaining

^{a 5 V}

supply,

^{it will}

become more and more difficult to reduce the power

dissipation

^{without further}

reducing

^the

Vcc.

3. Submicrometer transistor characteristics.

As device dimensions continue to shrink to the submic-

ron

level,

^{concerns arise} that such devices will no

longer

^{be able to withstand} the enhanced electric fields

imposed by

^{a 5 V power}

supply.

^In

^fact,

hot-carrier

injection

^{and the}

possibility

^of

performance degradation

associated with it have been

reported

^{even for DRAM}

as small as 64 kb

[20].

^{As a}

result,

stress-immune device structures

[21]

^{such as}

As-P

double diffused drain

(DDD)

^and

lightly doped

^drain

(LDD)

^{have been}

intensively

^{studied and}

applied

^to actual 1 Mb

chips [5].

Even if future

developmental

^{efforts are focused on the}

pursuit

^{of other new submicron}

devices,

^{it is}

possible

^to

assume that it will be inevitable to reduce the

Vcc,

^either

internally

^or

externally,

^{from the}

existing

5 V. This is

mainly

because it will be difficult to fabricate new stress-immune submicrometer devices which can withstand such

high supply voltage (5 V)

without

employing

very

complicated

^and

costly

proces-

ses. In

addition,

the relative conductance of such devices will be

higher

^{at a lower}

supply voltage [22].

4.

Memory

^cell

margin.

In the

light

^{of the}

previous arguments,

^{it seems}

appropriate

^to reduce the

supply voltage

^for

megabit

DRAMs.

However,

the

supply voltage

^is

strictly

^limited

by

the memory cell

margin.

^{The cell}

margin

^{can be}

roughly expressed

^{as the sum of the}

^noise, VN,

^caused

by

the electrical unbalance in the data line

itself,

^the

capacitive coupling

^{from the}

adjacent

data lines and a sense

amplifier

^offset

voltage,

and the stored

voltage degradations, VL

^and

V a,

^{due to}

^leakage

^{current and a}

particle, respectively,

^{as shown in}

figures

^{3 and 5.}

Fig.

^{5. -} Schematic SIN

design

for DRAM cell.

V p

⁼

V,/2:

^half

Vp precharge, V 0

⁼

V cc :

^{no limiter}

circuit.

In order to assure a sufficient cell

margin,

^a

higher supply voltage

^is

obviously

^better.

^Thus,

^{a further}

reduction in

supply voltage

necessitates the use of innovative cell structures which allow lower

VN, VL

and

V a.

^{To meet this}

requirement,

^a tremendous effort is

being

^{made to}

develop

^advanced memory cells

[23, 24]

^which exceed the

performance

^of

commercially accepted

memory cells.

Among

^{these new}

^cells,

^verti-

cally

structured cells

[1, 3, 4, 8-10, 25, 26] having high Cs

^{such as trench cells and stacked}

capacitor cells,

^are

becoming increasingly important.

^In

^addition,

^a

planar

cell structure combined with thin

Sio2

^film

operating

^at

half

VCC plate voltage [5, 6, 8,10,11]

^{is also}

extremely

efficient to obtain

high Cs.

^{A folded} data line cell

incorporating

^a multidivision data line and a half

ycc precharge provides

the lowest

VN.

^An

epitaxial layer [27]

^{and a stacked}

capacitor

^{cell are}

reported

^to

be effective in

reducing leakage

^{current. Note that the}

reduction of power

dissipation

is also essential for

reducing

^the

leakage

^current.

Many attempts

^{have been} made to increase soft error

immunity,

^that

^is,

^{to reduce}

the

critical, charge, Qc.

^These

^attempts

^{include the use}

of such structures as Hi-C

[28],

^an

epitaxial layer [29],

^a

buried

layer

^structure

[30]

^{and stacked}

capacitor [25].

The

p-channel

^MOS

switching

transistor cell

[17]

^em-

bedded in an n-well has also been

proposed

^{as another}

means of

reducing

^{the soft error.} In any event, ^{the main}

emphasis

^{must be}

put

^on the memory cell in order ^to reduce the

supply voltage.

5.

Perspective

^of power

supply voltage.

Continued _progress on the road toward

megabit

DRAMs will

surely require

^{a reduction in}

chip Vcc.

How far then

beyong

^{the 1 Mb DRAMs will a 5 V}

supply

^{survive ? This answer is}

highly controversial,

^as

can be

anticipated

^{from the}

previous

discussion. This is

because,

in addition to alternatives described

above,

there are incalculable unforeseen

developments

^{in the}

future. What makes the matter more

complicated

^{is the}

fact that device feature size tends to be

slightly larger

than one would have

expected.

^{This is} because the

chip

size can be seen to increase with every

generation.

^Data

obtained from actual

experimental

^NMOS

[1}

^and

CMOS

[4]

^{1 Mb}

chips (Table I)

^{seem to} be useful in

predicting

^{the next}

Vcc

level. Both

chips

^were

designed using

almost the same

layout

^{rules to cover some}

techniques

^{which are}

thought

^{to be useful} in the future for low power,

high

transistor

reliability

^{and a wide}

operating margin

for memory cells.

Anticipated

power

dissipations

^for

megabit DRAMs,

^{based on the}

design

data from

chips

^{in table}

I,

^{are shown} with dashed lines in

figure

^{1. The}

following assumptions

^{are made : the}

use of such circuit

techniques

^{as a half}

Vcc precharge

and a multidivision data line as shown in table

1 ;

increase in

chip

size of 1.5 times for every successive

generation ;

^{the use of the}

simply

scaled-down devices and memory ^cells

having

^a sufficient break down

voltage

^{and a wide}

operating margin, respectively.

^It

can be seen that CMOS offers the best solution.

However,

^at

_present,

^{even CMOS will not be able to}

handle the

higher

power

dissipation

ⁱⁿ

megabit

DRAMs unless the

supply voltage

is reduced and/or the number of refresh

cycle

^is increased. A critical

point

^for

the power

supply

transition is

thought

^{to be at the}

16 Mb level as far as power

dissipation

is concemed.

Note that the

development

^{of both} submicrometer transistors and memory cells ^{to meet} the

requirement

for such

high density

DRAMs will become more and

more

important. ^Hence,

^a 5 V power

supply might

survive even for the 4 Mb

generation through

^the

simultaneous advancement of process, device and cir- cuit

development

^{which are still not}

fully developed

ⁱⁿ

the 1 Mb

generation.

6. Conclusion.

It was shown that the

supply voltage

^is

closely

^{related to}

power

dissipation, reliability

and the memory cell

operating margin. Through discussion,

^{it was concluded}

that,

ⁱⁿ

spite

^of

CMOS,

^a transition from the

existing

supply voltage

^{of 5 V}

might

^{occur at} the 16 Mb level.

18

Table I. ^-

Performance comparison of

1 Mb NMOS and CMOS DRAMS.

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