Dynamic RAM

NEG Electronics Inc.

Dynamic RAM

Spring 1996 Data Book

Document No. M10547EJ4VODBU1

©1996 NEG Electronics Inc. All rights reserved.

Printed in the United States of America.

NEe

No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics Inc.

(NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALE ONLY, INCLUDING THE LIMITATION OF LIABILITY, WARRANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding information set forth herein or regarding the freedom olthe described devices from patent infringement. NECEL assumes no responsibility for any errors that may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor controklystems and life support systems. "Standard" quality grade devices are recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, anti·disaster and anti- crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliability requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death. "customers wish to use NECEL devices in applications not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL's willingness to support a given application.

i ,~ 11

Index

^{Iii '~}

ⁱ

!j

I.

'/

1

^~" ;

1 Selection Guide 11---

(I

1

"

11 ;1

!f 64MDRAM

Hyper Page Mode (EDO) 3.3V + 0.3V 1 - - - -

,

16M DRAM 5.0V + 10% 1 - - - - 115 ^,;,

3.3V + 0.3V

f - - -

263

4MDRAM 5.0V ± 1O%,5.0V ± 5% 455 1M DRAM 5.0V + 10% 1 - - - - 503

Fast Page Mode

I - - - , - - l

64M DRAM 3.3V + 0.3V

1 - - -

585

16M DRAM 5.0V + 10%

1 - - - -

671

3.3V + 0.3V

1 - - - -

773

4MDRAM 5.0V + 10%

1 - - -

875

I Synchronous DRAM 1-1--- ⁹⁷⁵

I How to Use DRAM 1-1--- ⁹⁸¹

NEC Semiconductor Device Reliability / Quality Control System 1 - - - - 1067

iii

iv

. . . . - - - NOTES FOR CMOS DEVICES - - - ,

<D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

® HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to Voo or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

@ STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc- tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

Contents

Selection Guide... ... ... 1 '1

DRAM ... 11

.uPD4264405, 4265405 ... 13

.uPD4264805, 4265805 ... 43

.uPD4264165, 4265165 ... 73

.uPD42S16405,4216405 ... 117

.u PD42S 17405, 4217405 ... 151

.u PD42S 17805, 4217805 ... 185

.uPD42S18165, 4218165 ... 219

.uPD42S16405L, 4216405L. .. 265

.uPD42S17405L, 4217405L. .. 299

.u PD42S 17805L, 4217805L ... 333

.uPD42S16165L, 4216165L. .. 367

.uPD42S18165L, 4218165L ... 411

5.0V + 10% .uPD42S421O, 424210 ... 457

5.0V + 5% 5.0V + 10% .uPD421805 ... 505

.uPD421165 ... 539

v

vi

Fast Page 1---rl64M DRAM 3.3V + O.3V .uPD4264400, 4265400 ... 587

3.3V + O.3V 5.0V + 10% .uPD4264800, 4265800 ... 611

.u PD4264160, 4265160 ... 635

.u PD42S 16400, 4216400 42S17400, 4217400 ... 673

.u PD42S 17800, 4217800 ... 703

.uPD42S18160, 4218160 ... 733

.uPD42S16400L,4216400L 42S17400L, 4217400L ... 775

.u PD42S 17800L, 4217800L ... 805

.uPD42S18160L, 4218160L ... 835

.u PD424400 ... 877

.u PD42S4800, 424800 ... 907

.u PD42S4260, 424260 ... 935

SynchronousDRAM ... .... ... ... ... .... ... ... ... 975

3.3V ± O.3V

L - - _ - - I 1-r---,-~.uPD4516421,

4516821, 4516161... 977

.uPD4516421-PC, 4516821-PC, 4516161-PC ... 979

How to Use DRAM ... 981

NEC Semiconductor Device Reliability / Quality Control System .... 1067

Selection Guide

2

Part Number

64MDRAM

,uPD42 64 40 5 LE - A 70

T] -- -.-- ^-r--.--

NECCMOS Dynamic RAM 64M Dynamic RAM, Refresh Cycle

64 : 8K Refresh 65 : 4K Refresh

Organization - - - ' 40: x4

80: x8 16: x 16

Function Mode - - - '

o : Fast Page Mode

5 : Hyper Page Mode (EDO)

P a c k a g e - - - -...

G5 : TSOP (II) (400 mil) LE : SO] (400 mil)

Vcc---~

A : 3.3V ± O.3V

Access T i m e - - - . . . I

16M DRAM

n ^V~~ Letter: 5.0V + 10%

L -A : 3.3V + 0.3V

,uPD42 S 16 40 5 L LE - A 70

NECCMOI

Dynamic RAM

S : Self Refresh - - - - ' No Letter: Non Self Refresh 16M Dynamic RAM,

- - - I

Refresh Cycle 16: 4K Refresh 17: 2K Refresh 18: lK Refresh

Organization - - - ' 40: x4

80: x 8 16: x 16

Function Mode - - - '

o : Fast Page Mode

5 : Hyper Page Mode (EDO)

Package - - - ' G3 : TSOP (II) (300 mil)

G5 : TSOP (II) (400 mil) LA : SOJ (300 mil) LE : SOJ (400 mil)

Access Time - - - 1

3

4

4MDRAM

(1) x 4 / x 8

JlPD42 S 4 80 0 LE - 70

NECCMOS---~I

Dynamic RAM

S : Self Refresh

---~

No Letter: Non Self Refresh 4M Dynamic RAM

Organization

---~

40: x4 80: x8

Function Mode ---'

o : Fast Page Mode

5 : Hyper Page Mode (EDO)

Package ---' GS : TSOP (II) (300 mil)

G5 : TSOP (II) (400 mil) LA : SO] (300 mil) LE : SO] (400 mil)

Access Time ---1

(2) x 16

,uPD42 S 4 2 10 LE - 70 - A

_____ ---11 -" -" ---

NECCMOS .

Dynamic RAM

S : Self Refresh _ _ _ _ _ _

- - - - l

No Letter: Non Self Refresh

4M Dynamic RAM ---....1

Refresh Cycle ---1

2 : 512 Refresh

Organization + Function Mode ---....1

10: x 16 + Hyper Page Mode (EDO) 60: x 16 + Fast Page Mode

Package _ _ _ _ _ _ _ _ _ _ _ _ _ _

^{- - - 1}

G5 : TSOP (II) (400 mil)

LE : SOJ (400 mil)

Access Time - - - ' Internal Control Code - - - '

5

6

1M DRAM

JlPD42 1 80 5 LE - 70 -A

NECCMOS---~I

Dynamic RAM

1M Dynamic R A M - - - ' Organization - - - '

80: x8 16: x 16

Hyper Page Mode (EDO) - - - ' P a c k a g e - - - '

05 : TSOP (II) (400 mil) LE : SO] (400 mil)

Access Time - - - '

Internal Control Code _ _ _ _ _ _ _ _ _ _ _ _

^--J

Synchronous DRAM

(1)x4/x8

,uPD45 16 8 2 1 G5 - A 10

NECCMOY

Synchronous DRAM Memory Density--...

16: 16M bits

Organization---' 4: x4

8: x8

No. of B a n k s - - - ' 2: 2 Bank

I n t e r f a c e - - - ' 1: LVTTL

P a c k a g e - - - -...

G5 : TSOP (II)

Vcr---'

A : 3.3V ± 0.3V

Minimum Cycle Time 10: 10 ns (100 MHz) 12: 12 ns (83 MHz) 13 : 13 ns (77 MHz) 15 : 15 ns (66 MHz)

7

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8

(2) x 16

IlPD45 16 16 1 G5 - A 10

NECCMOY

Synchronous DRAM Memory Density---'

16: 16M bits

Organization---' 16: x 16

No. of Banks & Interface ---....I

1 : 2 Bank, L VTTL

P a c k a g e - - - ' 05 : TSOP (II)

Vcc---~

A : 3.3V ± 0.3V

Minimum Cycle Time

10 : 10 ns (100 MHz)

12 : 12 ns (83 MHz)

13: 13 ns (77 MHz)

15 : 15 ns (66 MHz)

(3) x 4 / x 8 (For PC)

,uPD45 16 8 2 1 G5 - A 67 - PC

NECCMI

Synchronous DRAM

Memory Density - - - ' 16: 16M bits

Organization - - - ' 4: x4

8: x8

No. of Banks ---1

2: 2 Bank

Interface---...J 1: LVTTL

P a c k a g e - - - . . . J G5 : TSOP (II)

Vcc---~

A : 3.3V + 0.3V

For PC

Clock Frequency 83: 83 MHz 75: 75 MHz 67: 67 MHz 60: 60 MHz

9

10

(4) x 16 (For PC)

,uPD45 16 16 1 05 - A 67 - PC

NECCMOY

Synchronous DRAM Memory Density _ _

^---J

16: 16M bits

Organization

^---~

16: x 16

No. of Banks & Interface - - - - ' 1 : 2 Bank, L VTfL

P a c k a g e - - - ' G5 : TSOP (II)

V~---~

A : 3.3V ± O.3V

For PC

Clock Frequency

83: 83 MHz

75: 75 MHz

67: 67 MHz

60: 60 MHz

Hyper Page Mode (EDO)

64M Dynamic RAM

11

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NEe MOS INTEGRATED CIRCUIT

~PD4264405,4265405

64 M-BIT DYNAMIC RAM

16 M-WORD BY 4-BIT, HYPER PAGE MODE

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Description

The JlPD4264405, 4265405 are 16,777,216 words by4 bits CMOS dynamic RAMs with optional hyper page mode.

Hyper page mode is a kind of page mode and is useful for the read operation.

The JlPD4264405, 4265405 are packaged in 32-pin plastic TSOP(ll) and 32-pin plastic SOJ.

Features

• Hyper page mode

• Single +3.3 V±O.3V power supply

• 16,777,216 words by 4 bits organization

Part number Access time RN/ cycle time Hyper page mode

(MAX.) (MIN.) cycle time (MIN.)

~PD4264405-A50, 4265405-A50 50 ns 84 ns 20 ns

~PD4264405-A60, 4265405-A60 60 ns 104 ns 25 ns

~PD4264405-A70, 4265405-A70 70 ns 124 ns 30 ns

• CAS before RAS refresh, RAS only refresh, Hidden refresh

Part number Row address Column address Refresh Refresh cycle

~PD4264405 AO-A12 AO-A10 RAS only refresh, Normal Read / Write 8,192 cycles/64 ms CAS before RAS refresh, Hidden refresh 4,096 cycles/64 ms

~PD4265405 AO-A11 AO-A11 RAS only refresh, Normal Read / Write 4,096 cycles/64 ms

-

^-

CAS before RAS refresh, Hidden refresh

The information In this document is subject to change without notice.

Document No. M10856EJ2VODSU1

13

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~PD4264405,4265405

Ordering Information

Part number Access time

Package Refresh

(MAX.)

/LPD4264405G5-A50 50 ns

/LPD4264405G5-A60 60 ns

/LPD4264405G5-A70 70 ns 32-pin Plastic TSOP(II)

/LPD4265405G5-A50 50 ns (400miJ)

/LPD4265405G5-A60 60 ns

CAS before RAS refresh

/LPD4265405G5-A70 70 ns

/LPD4264405LE-A50 50 ns RAS on IV refresh

/LPD4264405LE-A60 60 ns Hidden refresh

/LPD4264405LE-A70 70 ns 32-pin Plastic SOJ

/LPD4265405LE-A50 50 ns (400 mil)

/LPD4265405LE-A60 60 ns

/LPD4265405LE-A'l0 70 ns

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~PD4264405,4265405

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Pin Configurations (Marking Side)

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32-pin Plastic TSOP (III (400 mill 32-pin Plastic SOJ (400 mill

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Vee

32 GND

^Vee

10 32 GND

1/01 2 1/04 1/01 2 1/04 i

1/02 3 1/03 1/02 3 1/03

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NC 4 NC NC 4 NC

NC 5

"l:"l:

NC NC 5

"l:"l:

NC .~

."." ."."

'1

NC 6

^{0 0}

... NC NC 6 ...

^{0 0}

NC

"

NN NN

CAS CAS

NC 7 "''''

^{en ....}

^{26 NC 7}

^{en ....}

"''''

WE

S ... ₂₅

_{OE WE}

_S .... ....

OE

0 0 0 0

en en en en

RAS _{AO 10} ""

^enen

^{A 12/NC}

^Note

RAS ⁹

^r-r-

^{mm A 12/NC}

^Not.

A11 AO 10 A11

Al 11 Al0 Al 11 Al0

A2 12 21 A9 A2 12 A9 i:

j'

A3 13 AS A3 13 AS

^"

..

A4 14 A7 A4 14 A7

A5 15 A6 A5 15 A6

Vee

16

17

GND

Vee

16 GND

Note A12 ... I1PD4264405 NC ... I1PD4265405

AO to A12 Address Inputs 1/01 to 1/04 Data Inputs/Outputs

RAS Row Address Strobe

CAS Column Address Strobe

WE Write Enable

OE Output Enable

Vee Power Supply

GND Ground

NC ·No Connection

15

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~PD4264405,4265405

Input/Output Pin Functions

The ¢'D4264405, 4266405 have input pins RAS, CAS, WE, QE, AddressNoU ' and input/output pins 001 to

V04.

Pin name Input!

Function Output

RAS Input RAS activates the sense amplifier by latching a row address and selecting a (Row address strobe) corresponding word line.

It refreshes memory cell array of one line selected by the row address.

It also selects the following function .

• CAS before RAS refresh

CAS CAS activates data input!output circuit by latching column address and (Column address strobe) selecting a digit line connected with the sense amplifier.

AD to AXNote , Address bus.

(Address inputs) Input total 24-bit of address signal, upper bits and lower bits in sequence (address multiplex method).

Therefore, one word is selected from S,3SS,60S-word by S-bit memory cell array.

In actual operation, latch row address by specifying row address and activating RAS.

Then, switch the address bus to column address and activate CAS.

Each address is taken into the device when RAS and CAS are activated.

Therefore, the address input setup time (WR, tAse) and hold time (tRAH, tCAH) are specified for the activation of RAS and CA~.

WE Write control signal.

(Write enable) Write operation is executed by activating RAS, CAS and WE ..

OJ:

Read control signal.

(Output enable) Read operation can be executed by activating

RAS,

CAS and OE.

If WE is activated during read operation, OE is to be ineffective in the device.

Therefore, read operation cannot be executed.

1/01 to V04 Input! 4-bit data bus.

(Data inputs/outputs) Output I/O 1 to V04 are used to input/output data.

Note1.

Part number Address inputs Upper bits Lower bits

I1PD4264405 AO-A12 13 11

I1PD4265405 AO-A11 12 12

Hyper Page Mode

The hyper page mode is a kind of page mode with enhanced features. The two major features of the hyper page mode are as follows.

1. Data output time is extended.

In the hyper page mode, the output data is held to the next CAS cycle's falling edge, instead.of the rising edge. For this reason, valid data output time in the hyper page mode is extended compared with the fast page mode (=data extend function). In the fast page mode, the data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in the hyper page mode, the timing margin in read cycle is lager than that of the fast page mode even if the CAS cycle time becomes shorter.

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Hyper Page Mode

The hyper page mode is a kind of page mode with enhanced features. The two major features ofthe hyper page mode are as follows.

1. Data output time i. extended.

In the hyper page mode, the output data is held to the next CAS cycle's falling edge, instead of the rising edge. For this reason, valid data output time in the hyper page mode is extended compared with the fast page mode

(=

data extend function). In the fast page mode, the data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in the hyper page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time bec~mes ^shorter.

2. The CAS cycle time in the hyper page mode i. shorter than that in the fast pege mode.

In the hyper page mode, due to the data extend function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same.

Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that in the fast page mode is 40 ns.

In the hyper page mode, read (data out) and write (data in) cycles can be executed repeatedly during one RAS cycle. The hyper page mode allows both read and write operations during one cycle, but the performance is equivalent to that of the fast page mode in that case.

The following shows a part ofthe hyper page mode read cycle. Specifications to be observed are described in the next page.

V,H- RAS V,L-

Address V,H- V,L-

WE V,H-

V,L-L..c...c~-L..J

Hyper Page Mode Read Cycle

tOCH tOEA

tm

VOH- Hi-Z

1/0 VOL- .---

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~PD4264405,4265405

Cautions when using the hyper page mode

1. CAS

access should be used to operate tHPC at the MIN. value.

2.

To make I/Os to Hi-Z in read cycle, it is necessary to control RAS,

CAS,

WE, OE as follows. The effective specification depends on the state of each signal.

(1)

Both RAS and

CAS

are inactive (at the end of read cycle)

WE: inactive, 5!: ^active

tOFC is effective when

RAS

is inactivated before

CAS

is inactivated.

tOFR is effective when CAS is inactivated before

RAS

is inactivated.

(2)

Both RAS and

CAS

are active or either

RAS

or

CAS

is active (in read cycle) WE, OE: inactive ..•.. tOEZ is effective.

(3)

Both

RAS

and

CAS

are inactive or

RAS

is active and

CAS

is inactive (at the end of read cycle) WE, OE: active and either tRRH or tRcH must be met ... twEZ and twpz are effective.

3.

In read cycle, the effective specification depends on the state of

CAS

signai when controlling data output with the OE signal.

(1) CAS:

inactive, OE: active ... tCHO is effective.

(2) CAS,

OE: active ... tOCH is effective.

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Electrical Specifications

• All voltages are referenced to GND .

• After power up, wait more than 100 #'S(RAS, ~ inactive) and then, execute eight CAS before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings

Parameter Symbol Condition Rating Unit

Voltage on Any Pin Relative to GND VT -0.5 to +4.6 V

Supply Voltage Vee -0.5 to +4.6 V

Output Current

10

20 mA

Power Dissipation

Po

1 W

Operating Ambient Temperature TA

o

to +70 ·C

Storage Temperature Til; -55 to +125 ·C

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to

be

operated under conditions outsida the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect devica reliability.

Recommended Operating Conditions

Parameter Symbol Condition MIN. TYP. MAX. Unit

Supply Voltage Vee 3.0 3.3 3.6 V

High Level Input Voltage VIH 2.0 Vee +0.3 V

Low Level Input Voltage VIL -0.3 +0.8 V

Operating Ambient Temperature TA 0 70 ·C

Capacitance

(TA

= 25°C, f = 1 MHz)

Parameter Symb.ol Condition MIN. TYP. MAX. Unit

Input Capacitance CI1 Address 5 pF

CI2 RAS, CAS,

WE, OE

7 pF

Data Input/Output Capacitance Cvo I/O 7 pF

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~PD4264405,4265405

DC Characteristics (Recommended Operating Conditions unless otherwise noted)

[~PD4264405J

Parameter Symbol Test condition MIN. MAX.

Operating current Iccl RAS, CAS Cycling tRAC - 60 ns 100

tRC = tRcIMIN.) tRAC = 60 ns 90

10= 0 mA tRAc = 70 ns 80

Standby current Icc2 RAS, CAS ii= VIH IMIN.) 10 = 0 mA 1.0

RAS,

CAS ii= Vcc -0.2 V 10=OmA 0.6 RAS only refresh current Icca

RAS

Cycling tRAC = 60 ns 100

CAS ii= VIH IMIN.) tRAC = 60 ns 90

tAc ,= tRC IMIN.) 10=0 mA tRAC = 70 ns 80

Operating current Icc4 RAS ~ VllIMAX.) tRAC = 60 ns 100

(Hyper page mode) CAS Cycling tRAC = 60 ns 90

tHPC =' tHPC IMIN.) 10=OmA tRAC = 70 ns 80

CAS before RAS Iccs WCycling tRAC = 50 ns 130

refresh cu rrent _tRC = tRC IMIN.) tRAC = 60 ns 110

10 = 0 mA tRAC = 70 ns 100

VI = Oto 3.6 V

Input leakage current II Il) all other pins not under test = 0 V -6 +5 Output leakage current _lOlL) Vo = 0 to 3.6 V

Output is disabled (Hi·Z) -6 +5

High level output voltage _VOH 10 =-2.0 mA 2.4

Low level output voltage VOL 10 = +2.0 mA 0.4

Unit Notes mA 1,2,3

mA mA 1,2,3,4

mA 1,2,6

mA 1,2

ItA

ItA

V V

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~PD4264405,4265405

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Parameter Symbol Test condition MIN. MAX. Unit Notes

Operating current Icc I RAS, CAS Cycling tRAC - 60 ns 130 mA 1,2,3

tRC = tRcIMIN.! tRAC. 60 ns 110

10.OrnA tRAC - 70 ns 100

Standby current Icc2 RAS, CAS S; VIH IMIN.! 10-0 mA ·1.0 mA

RAS,

CAS S; Vcc - 0.2 V 10- OmA 0.6

RAS only refresh current Icca RAS Cycling tRAC - 60 ns 130 mA 1,2,3,4

CAS S; VIH IMIN.! tRAC. 60 ns 110

tRC = tRC IMIN.! 10 = 0 mA tRAC = 70 ns 100

Operating current IcC4 RAS ;:ii! VIL IMAX.! tRAC = 60 ns 100 mA 1,2,6

(Hyper page mode) CAS Cycling tRAC = 60 ns 90

tHPc = tHPC IMIN.! 10=OmA tRAC = 70 ns 80

CAS before RAS Iccs ~Cycling tRAC = 60 ns 130 mA 1,2

refresh current tAc = tRC IMIN.) tRAc = 60 ns 110

10 = 0 mA tRAC = 70 ns 100

VI = Oto 3.6 V

Input leakage current II IL! all other pins not under test

=

^{0 V -6 +6 jJA}

Output leakage current lOlL) Vo = Oto 3.6 V

Output is disabled (Hi-Z) -6 +6 jJA

High level output voltage VOH 10 =-2.0 mA 2.4 V

Low level output voltage VOL 10 = +2.0 mA 0.4 V

Note. 1. ICCI, Icca, Icc4 and Iccs depend on cycle rates (tRc and tHPC).

2. Specified values are obtained with outputs unloaded.

3. IccI and Icc3 are measured assuming that address can be changed once or less during RAS ~ VILIMAX.! and CAS S; VIHIMIN.).

4. Icca is measured assuming that all column address inputs are held at either high or low.

5. icC4 is measured assuming that all column address inputs are switched only once during each hyper page cycle.

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~PD4264405,4265405

AC Characteristics

(Recommended Operating Conditioll8

unl_

otherwi . . noted) AC Characteristics Teet Condition.

(1) Input timing specification (2) Output timing specification

VIH (MIN.)

=

2.0 V

---~

VIL (MAX.) = 0.8 V --- ... -::.:.;;/_ _I

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tr';'

2

ns tr~

^2'

^ns

V~ (MIN.) == 2.0 V ---~ } -

VOL (MAX.)

=

0.8 V

---~'-

^{_ _ _ -...J}

(3) Loading conditions are 100 pF + 1 TTL,

Common to R . . d, Write, Read Modify Write Cycle

tRAC" 60 ns tRAC = 60 ns tRAC" 70 ns

Parameter Symbol Unit Notes

MIN. MAX. MIN. MAX. MIN. MAX.

Read I Write Cycle Time tRC 84

-

¹⁰⁴

-

¹²⁴

-

^ns

RAS Precharge Time tRP 30

-

⁴⁰

-

⁶⁰

-

^ns

CAS Precharge Time tCPN 7

-

¹⁰

-

¹⁰

-

^ns

RAS Pulse Width tRAS 60 10000 60 10000 70 10000 ns

CAS Pulse Width tCAS 7 10000 10 10000 12 10000 ^{. ns}

RAS Hold Time tRSH 10

-

¹⁰

-

¹²

-

^ns

CAS Hold Time tCSH 38

-

⁴⁰

^-

⁶⁰

^-

^ns

RAS to CAS Delay Time tRCO 11 37 14 45 14 62 ^ns 1

RAS to Column Address Delay Time tRAD 9 25 12 30 12 36 ns 1

CAS to RAS Precharge Time tCRP 5

-

⁵

^-

⁵

^-

^{n. 2}

Row Address Setup Time tAsR 0

-

⁰

-

⁰

-

^ns

Row Address Hold Time tRAH 7

-

¹⁰

-

¹⁰

-

^n.

Column Address Setup Time lAsc 0

-

⁰

-

⁰

^-

^ns

Column Address Hold Time tCAH 7

-

¹⁰

-

¹²

-

^.ns

OE Lead Time Referenced to RAS tOEs 0

-

⁰

-

⁰

-

^ns

CAS to Data Setup Time tCLZ 0

-

⁰

-

⁰

-

^ns

OE to Data Setup Time toLZ 0

-

⁰

-

⁰

-

^n.

OE to Data Delay Time tOED 10

-

¹³

-

¹⁶

-

^ns

Transition Time (Rise and Fall) tT 1 50 1 60 1 60 ns

Refresh Time tREF

-

⁶⁴

-

⁶⁴

-

^{64 ms}

22

NEe JlPD4264405,4265405 It :~

---::---:...---'o

Not.. 1. For read cycles, access time is defined as follows:

Input Conditions Acees.Time Aceess Time from RAS

tRAD:Ii! tRAD (MAX.) end tRCD:Ii! tRCD (MAX.I tRAC (MAX.I tRAC (MAX.) tRAD> tRAD (MAX.) and tRCO:li tRco (MAX.) tAA(MAX.) tRAD + tv. (MAX.) tRCD > tRCD (MAX.I tCAC (MAX.) tRcO + tCAC (MAX.I

tRAO(MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters. They are used to determine which access time (tRAc, tAA or tCAC) is to be used for finding out when output data will be available. Therefore, the input conditions tRAD

ii:

tRAO(MAX.) and tRCO i:

tRCD(MAX.) will not cause any operation problems.

2. tCRP(MIN.1 requirement is applied to RAS, CAS cycles.

Reid Cycle

tRAC. 50 ns tRAC. 60 ns tRAC. 70 ns

Parameter Symbol Unit Notes

MIN. MAX. MIN. MAX. MIN. MAX.

Access Time from RAS tRAC

-

⁶⁰

-

⁶⁰

-

^{70 ns 1}

Access Time from CAS tCAC

-

¹³

-

¹⁶

-

^{18 ns 1}

Access Time from Column Address tAA

-

²⁶

-

³⁰

-

^{36 ns 1}

Access Time from OE tOEA

-

¹³

-

¹⁶

^-

^{18 os}

Column Address Lead TIme Referenced to RAS tRAL 26

-

30

-

³⁶

-

^ns

Read Command Setup Time tRCS 0

-

⁰

-

⁰

-

^ns

Read Command Hold Time Referenced to RAS tRRH 0

-

⁰

-

⁰

-

^{ns 2}

Read Command Hold TIme Referenced to CAS tRCH 0

-

⁰

-

⁰

^-

^{ns 2}

Output Buffer Turn·off Delay Time from OE tOEZ 0 10 0 13 0 16 ^ns 3

CAS Hold Time to OE tCHO 6

-

6 ^{- '} 6

-

ⁿ⁸

Not.. 1. For read cycles, access time is defined as follows:

Input Conditions Access Time Access Time from RAS

tRAD;:a; tRAD (MAX.) and tRCD;:a; tRCD (MAX.) .t RAC (MAX.) tRAC (MAX.) tRAD> tRAD (MAX.I and tRCD;:ii tRCD (MAX.) tAA(MAX.) tRAD + tAA (MAX.I

tRCD > tRCD (MAX.) tCAC (MAX.I tRCD + tCAC (MAX.)

tRAO(MAX.1 and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output data will be available. Therefore, the input conditions tRAD 5; tRAO(MAX.1 and tRCD

ii:

tRCD(MAX.1 will not cause any operation problems.

2. Either tRCH(MIN.) or tRRH(MIN.1 should be met in read cycles.

3. tOEZ(MAX.1 defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or VOL.

23

24

NEe

~PD4264405,4265405

Write Cycle

tRAc.50 ns tRAC. 60 ns tRAc.70 ns

Parameter Symbol

MIN. MAX. MIN. MAX. MIN. MAX. Unit Notes

WE Hold Time Referenced to CAS twCH 7

-

¹⁰

-

¹⁰

-

^{ns 1}

WE Pulse Width twp 7

-

¹⁰

-

¹⁰

-

^{ns 1}

WE Lead Time Referenced to RAS tRWL 10

-

¹⁰

-

¹²

-

^ns

WE Lead Time Referenced to CAS tCWL 7

-

¹⁰

^-

¹²

^-

^ns

WE Setup Time twcs 0

-

⁰

-

⁰

-

^{ns 2}

OE Hold Time tOEH 0

-

⁰

-

⁰

-

^ns

Data-in.Setup Time tDs 0

-

⁰

-

⁰

-

^{ns 3}

Data-in Hold Time tDH 7

-

¹⁰

-

¹⁰

-

^{ns 3}

Not.. 1. twPIMIN.1 is applied to late write cycles or read modify write cycles. In early write cycles, twcHIMIN.1 should be met.

2. If twcs

s:

twcslMIN.I, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.

3. tOSIMIN.1 and tDHIMIN.1 are referenced to the CAS falling edge in early write cycles. In late write cycles and read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle

tRAC. 60 ns tRAC. 60 ns tRAC. 70 ns

Parameter Symbol

MIN. MAX. MIN. Unit Notes

MIN. MAX. MAX.

Read Modify Write Cycle Time tRWC 107

-

¹³³

-

¹⁶⁷

^-

^ns

RAS to WE Delay Time tRWO 64 - 77

-

⁸⁹

-

^ns 1

CAS to WE Delay Time tCWD 27

-

³²

-

³⁷

-

^{ns 1}

Column Address to WE Delay Time tAwo 39

-

⁴⁷

-

⁵⁴

-

^{ns 1}

Not. 1. If twcs

s:

tWCSlMIN.1 the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle. If tRWD

s:

tRWDIMIN.I, tCWD

s:

tCWDlMIN.I, tAWO

s:

tAwoIMIN.I, and tCPWD iii; tCPWDlMIN.I, the cycle is a read modify write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is met, the state of the data out is indeterminate.

___ N_E_C _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...;IJ.;...P_D42 _ _ 6440 _ _ 5_,_42_6_540 _ _ 5_~--'

Hyper 'age Mode 'I

tRAC. 60 na tRAc.60 ns tRAC .70 na

Parameter Symbol

MIN. MAX. MIN. MAX; MIN. MAX. Unit Notei

Read I Write Cycle Time tlf'C 20

-

26

-

³⁰

-

^{na 1}

iiAS

Pulse Width tRAIl' 60 126000 60 2600( 70 26001 ns

CAS Pulse Width tHcM 7 10000 10 10000 12 10000 ns

CAS Precharge Time tcp .7

-

¹⁰

-

^{10 ~ ns}

Access Time from CAS Precharge lAcP

-

³⁰

-

³⁶

-

^{40 na}

CAS Precharge to WE Delay TIme tCPWD 41

-

⁶²

-

⁶⁹

^-

^{ns 2}

RAS Hold TIme from

CAS

Precharge tRHCP 30

-

³⁶

-

⁴⁰

-

^na

Read Modify Writa Cycle Time tHPRWC 62

-

⁶⁶

-

⁷⁶

-

^ns

Data Output Hold Time tDHc 6

-

⁶

-

⁶

-

^n.

OE to CAS Hold Time tOCH 6

-

⁶

-

⁵

^-

^n.

OE Precharge Time toeP 6

-

⁶

-

⁶

-

ⁿ⁸

Output Buffer Turn-off Delay from WE lwEz 0 10 0 13 0 16 ns 3,4

WE Pulse Width twpz 7

-

¹⁰

-

¹⁰

- ^n.

⁴

Output Buffer Turn-off Delay from RAS tOFR 0 10 0 13 0 16 ns 3.4

Output Buffer Turn-off Delay from CAS tOFC 0 10 0 13 0 16 ns 3.4

tHPCIMIN.1 is applied to access time from CAS Note. 1.

2.

If twcs !1: twCSIMIN.I, the cycle is an early write cycle and the data out will remain Hi - Z through the entire cycle. If tRWD

s::

tRWDCMIN.I, tCWD ~ tcwDCMIN.I, tAWD ~ tAWDCMIN.I, and tCPWD ~ tCPWDIMINJ, the cycle is a read modify write cycle and the data out will contain data read from the selected cell.

If

neither of the above conditions is met, the state of the data out is indeterminate.

3. tOFCIMAX.I, tOFRIMAX.1 and twEZIMAX.1 define the time when the output achieves the condition of Hi-Z and is not referenced to VOH or VOL.

4. To make II0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective specification depends on state af each signal.

(1) RAS, CAS : I~active (at the end of read cycle) WE: inactive, OE: active

tOFC is effective when RAS is inactivated before CAS is inactivated.

tOFR is effective when CAS is inactivated before RAS is inactivated.

(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle) WE : inactive, OE : inactive ... tOEZ is effective.

--- --- --- ---

(3)· Both RASand CAS are inactive or·RAS is active and CAS·is·inactive (at the end of read cycle)

WE,OE:active and either tRRH or tRCH must be met .. • lwEz, tWPz are effective.

25

II _,

:~

I

t

1

I _i

!

'. ₁

I:!

i:

,I

11

II I:

J

NEe

~PD4264405,4265405

Refresh Cycle

tAAc - 50 ns tAAc.60 n8 tAAC" 70 n8

Parameter Svmbol

MIN. MAX. MIN. MAX. MIN. MAX. Unit Note

~SetupTime tCBA 5

-

⁵

-

⁵

^-

^ns

~ Hold Time ~ before

RAS

Refresh) tCHR 10

-

^10'

-

¹⁰

-

^ns

RAS

Precharge ~ Hold Time tApe 5

-

⁵

-

⁵

-

^ns

WE Setup Time twsR 10

-

¹⁰

-

¹⁰

-

^ns

WE Hold Time twHR 15

-

¹⁵

-

¹⁵

-

^ns

26

I~

NEe yPD4264405, 4265405 :;

---.;;.,.;;;;.;:::::;.;=---';.;.;;....;;....;.;;;;.;...,;...;;...;;..;;...<..-.;;;;.;;;;...;;....;;..;..,;;;..---.~

Read Cycle

IRe

RAS

^VIH-_V,L-

tCSH

CAS

_V,L-^V,H-

Address V,H- V,L-

DE V,H-

V,L- - ...

t-' ... +-..., ... -+ ... ""'"-' ... +-:---;-t---''"t''r---t-' ...

~

tCAe

tell

tOll

tOFR

Vot<- Hi· Z

I/O Vrx- •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• Data out Hi·Z

27

i~

:~

Ii

II

I'i';

j

I'i'

'i I

1:1

.~

!

NEe yPD4264405,4265405

Early Write Cycle

tAc

tFIAS tAp

RAS

^{V, ...}

V,L-

tcSH

CAS

^V,ii-

V,L-

Address V, ...

V,L-

1/0 V,ii-

V,L- ... ...,"-" ... .-.;..., "--_ _ _ _ _ _ _ _ ....JI " - ' ... ""'-'~ ... ...

Remark

DE: Don't care

28

,I

~~

_ _ .:..:N::.::E==C=--_ _ _ _ _ _ _ _ _ _ _ _ _ _ ...r:.Il::.P..::;D;...;;4~26;:;..44.:....;;.;:0;.:.5:..., 4.:.,:2:.:6:;:5:...:.4.;;.;05::;..-. _ _ _ :,1

Lite Write Cycle

If<:

lRAS

I ,I~

Address

29

30

NEe

Read Modify Write Cycle

Address

WE

OE

VO

VO V,ii- V,l-

V,ii- V,l-

V,ii- VIl-

V,ii- VIl-

V,ii- VIl-

VOIi- VOl-

tACO

~---

Hi-Z

-

gPD4264405,4265405

tRWe tAAs

teSH

!ASH

tOEA tOEH

tCAe tos toH

--- - ^{Data in}

tOLZ

Hi-Z

--.---_.

"

1

_ _ .;..N __ E~C~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ... JL=P...;;;;D __ 4=2.;;.,64.;..4.;.;0;..;;;.5..:..., ...;;.,;42=6;;.,;;5 __ 4.;;.,05;;;...' _ _ _ If I

Hyper Paga Mode Raad Cycle

RAS

CAS

Address

WE

OE

VO VIH- VIL-

V'H- VIL-

VIH- V'L-

VIH- VIL-

V'H- VIL-

VOH- VOL-

tcSH

~

^{IRCD tHCAS}

J _e~~~

^~

"

~~

IR~

/////fl '

\\\\\\\\\\~ _{I I}

tRAc

L

^fAA

teAe

~

-- --- --- --- --- _til :J.. ___ --- -1~

IRAsp IRp

IRHCf' ~

tHPC IRSH

' -

~

^tHCAS

1~

^tHCAS

YI ^~

r - ,

- ^J

^tcFR

'-

~~ ^~ Ci

^toFe

~

^Col.

l® ^:)

^Col.

XXX X.

~

fo-

RH ~

'\ }i/

tAcP tAcp

~ ^~

fAA fAA

teAe teAe

/ \\ .\

~ ~ ^toez

Data out

--0

^{Data out ~--{)l Data out}

---

Remark

In the hyper page mode, read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle.

31

32

NEe yPD4264405,4265405

Hyper Page Mode R.ad Cycl.IWE Control!

tRHCP

tCSH

Address V,H- V,L-

WE ^V,H-_V,L-

OE ^V,H-_V,L-

I/O VOH- •••••••••••••••

':I1:.Z .•••..•••..

VOL-

^{Data out}

Remark In

the hyper page mode, read, write and read modify write cycles are available for each of the

consecutive CAS cycles within the same RAS cycle.

1',* .~

NEe ,uPD4264405,4265405!

- - - . . . ; ; . . . . ; ; ; ; . . : : : ; ; . ; : : : : ; . . , - - - -... =...;;;;...;;.;;;;.;;;...;;~;;.;;;~..;:.;;;=.~=.~---~

!

Hyper Page Mode Read Cycle 1i5E Control)

tAASP

- - " tAHOP

~

teSH tHPC tRSH

~

^{tAco tHCAS}

^~

^tHeAS

^~

^tHCAS

r-4

J ^\\

^r----,

^{r----.. / J \.-}

~

^tAAt

~

^Row

^~~

^ColA

m ^~

^~~ C O l . s m ).

^~~

CoI.C

XXX ¹⁺ ~

^tOFR

I

tAAe

.. ~H

tAA tAA

t A f - I

~ ~

^tOES

^{.... ---1}

^tRRI-

Address V,H- V,l-

WE

/////!

^{teHo tOCH} tcHO ^{J!;AC tAA}

\\\\

i-

toeH lACp lACp

tOEA ~

~

^{~ ~}

^~

\\\\\\\\\\\ -

^,.--,

...

\~\\

/ \..

^{I - -}

~

^OEA

^V

~ ~ ^tell

-!2!4

tOEZ ,...!2g.."

~ "'I-io--

^~

VO

VOH-

VOL-

__________

~;l___________ ~~

----

~

^{Oata out}

B)---1~

^{Data out B}

---1~

^{Data out C}

^__

^11!;~_

Remark

In the hyper page mode, read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle.

33

t ,

.1 It ,t

',fl.

34

NEe

HPD42~4405,4265405

Hyper Pa". Mode Early Writ. Cycl.

Address

VII.- VIL-

Remarks

1. OE: Don't care

2. In the hyper page mode, read, write and read modify write cycles are available for each of

the consecutive CAS cycles within the same RAS cycle.

If

NEe gPD4264405. 4265405 !~ 'i

----~~~~~---~-~~~~~~~~~~---~.~

Hyper Page Mode Lete Write Cycle

Remark

In the hyper page mode, read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle.

35

( i ~

I ':~

NEe

Hyper Paga Mode RNd Modify Write Cycle

V,ii- VIL-

V,ii- VIL-

yPD4264405,4265405

Address V,ii- VIL-

36

V,ii- VIL-

V,ii- VIL-

I/O VOl<-

VOL-

I/O V,ii- VIL-

Remark

In the hyper page mod", read, write and read modify write cycles are available for each of the

consecutive CAS cycles within the same RA5 cycle.

I

:.,t

_ _ :....;N;;;.;E=:;C=-_ _ _ _ _ _ _ _ _ _ _ _ _ _

....r;.Il;.;..P..;;;.D...;.42;;;.;6;..;4;...;;4..;;..05;;.::,...;4:.;::2;.;:.65;:;..4.:..;:O:.;::5 _ _ _

~if

Hyper Paga Moda R.ad and Writa Cycla

v .. - CAS

VIL-

Address V,H- VIL-

WE ^VI~-_V,L-

OE ^V,H-_V,L-

VOH- Hi-Z

tcsH

I/O

v

01.-

•••••••••••••••••••••••••••••••• '

I/O

1AAsp

tRHCP

•••••••••• I:!l :l-•••..•••.•••••.

Ramark

In the hyper page mode, read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same 'RAS cycle.

'I'

37

NEe gPD4264405,4265405

CAS Before RAS Refresh Cycle

tRAS

Remark

Address, OE: Don't care I/O: Hi·Z

RAS Only Refresh Cycle

tRAS tRP

teAP

Address V,,·

Remark

WE, OE: Don't care I/O: Hi·Z

38

_---.,;N~E;;;..C.=_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..,t;,,;El_P.;;...D4 __ 2 .... 6 __ 4_40_5 __ ,_4_2_65_4_0_5 _ _ _ _ ,11 t

Hidden Ref ... Cycle (Read)

RAS

v .. - v .. -

CAS V,H- V,L-

Address V,H- V,L-

WE VIH- VR.-

tAco

IRC tAe

lRAS lAAS

tRSH ICHR I"",

DE

V,H-

V,L- ---:1....J>....l.-l...l...Tlo....:l....J...I"-t-l...l...l..r~~=---+,...--..t...I-1--....l....\....l...~~:....rl....J...I-

VOH- Hi-Z

110 Vcx.- ---

Data

out Hi-Z

" ,'~

;,

I t I

39

40

NEe

Hidden Refresh Cycle (Write)

Address

va

V,H- VIl-

V,H- VIl-

V,H-

tAC tAAs

VIl- ^--J ... .,... _ _

+_I---',...J

V,H-

VIl- L...l ... ' - " ... ...IL.. ... "-..l ... ~ 1\. _ _ _ _ --"

Remark OE: Don't care

yPD4264405,4265405

tAC

tAAS

I, ,y

_...!N~E:=::C~ _ _ _ _ _ _ _ _ _ _ _ _ _ --.s::.y:.:..P=-D..:.:42=.:::6:...;;4..:.40=.:::5;.:.,...:.4=26::;.;:5;...;;4~O5~ ^{_ _ _ :1}

Package Drawings

32PIN PLASTIC TSOP(II) (400 mil)

32

-++---+---t-

~h~luuu~t~t'oOJ~

01$1

^M

@I

NOTE

Each lead centerline is located within 0.21 mm (0.009 inch) of its true position (T.P.) at maximum material condition.

detail of lead end

~Jmmmm

H ^I

^mmm .~ ^J

L

ITEM MILLIMETERS INCHES A 21.17 MAX. 0.834 MAX.

B 1.075 MAX. 0.043 MAX.

C 1.27 (T.P.) 0.050 (T.P.)

0 0.42~8:89 0.017±0.003 I':

E 0.1:t0.05 0.004%0.002

F 1.2 MAX. 0.048 MAX. ^,I

I,'

G 0.97 0.038

H 11.76:t0.2 0.463:t0.008 10.16:t0.l 0.400:1:0.004 0.8:1:0.2 0.031 ~8:883

K 0.145~8:8~g 0.006:t0.00l L 0.5:t0.l 0.020:8:88~

M 0.21 0.009

N 0.10 0.004

P 3⁰+70

-3' ^30+7• -3' S32G5-50-7 JD2

41

42

NEe yPD4264405,4265405

32 PIN PLASTIC SOJ (400

mill

- t t - - - + - - - i - U Q

NOTE

Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maxi- mum material condition.

16 E

ITEM 8 C 0 E F G H

J K

,

M N P Q T U

MILLIMETERS 21.06:0.2 10.16 11.18:0.2 1.005:0.1 0.74 3.5:0.2 2.545:0.2 0.8 MIN.

2.6 1.27 (T.P.) 0.40:0.10 0.12 9.4:0.20 0.1 R 0.85 0.20:8~g

P32LE-400A INCHES i 0.829:0.008

i

0.400

I

0.440:0.008

I

0.040:8:g~ ^I :

I

^0.029

!

0.138:0.008 0.100:0.008 0.031 MIN.

0.102 0.050 (T.P.) 0.016:8gg~

0.005 0.370:0.008 0.004 R 0.033 0.008:8gg~

~

',i!,

r--- PRELIMINARY DATA SHEET

I'

NEe MOS INTEGRATED CIRCUIT

~PD4264805,4265805

64 M-BIT DYNAMIC RAM

8 M-WORD BY 8-BIT, HYPER PAGE MODE

- - - -_ _ _ _ _ _

I~

Description

The IlPD4264805, 4265805 are 8,388,608 words by 8 bits CMOS dynamic RAMs with optic;mal hyper page mode.

Hyper page mode is a kind of page mode and is useful for the read operation.

The IlPD4264805, 4265805 are packaged in 32-pin plastic TSOP(lI) and 32-pin plastic SOJ.

Features

• Hyper page mode

• Single +3.3 V±0.3V power supply

• 8,388,608 words by 8 bits organization

Part number Access time

RJW

cycle time Hyper page mode

(MAX.) (MIN.) cycle time (MIN.)

I'PD4264805-A50, 4265805-A50 50 ns 84 ns 20 ns

I'PD4264805-A60, 4265805-A60 60 ns 104 ns 25 ns

I'PD4264805-A70, 4265805-A70 70 ns 124 ns 30 ns

• CAS before RAS refresh, RAS only refresh, Hidden refresh

Part number Row address Column address Refresh Refresh cycle

I'PD4264805 AO-A12 AO-A9 RAS only refresh, Normal Read / Write 8,192 cycles/64 ms CAS before RAS refresh, Hidden refresh 4,096 cycles/64 ms I'PD4265805 AO-A11 AO-A10 RAS only refresh, Normal Read / Write 4,096 cycles/64 ms

CAS before RAS refresh, Hidden refresh

--

The information In this docum.nt Is sublect to chang. without notlc •.

Document No, M10857EJ2VODSU1

II

:1

"II

43

NEe

~PD4264805,4265805

Ordering Information

Part number Access time

Package Refresh

(MAX.)

~PD4264805G5-A50 50 ns

~PD4264805G5-A60 60 ns

. ~PD4264805G5-A70 70 ns 32-pin Plastic TSOP(II)

~PD4265805G5-A50 50 ns (400 mil)

~PD4265805G5-A60 60 ns

CAS before RAS refresh

~PD4265805G5-A70 70 ns

RAS only refresh

~PD4264805LE-A50 50 ns

60 ns Hidden refresh

~PD4264805LE-A60

~PD4?64805LE-A70 70 ns 32-pin Plastic SOJ

~PD4265805LE-A50 50 ns (400 mil)

~PD4265805LE-A60 60 ns

~PD4265805LE-A70 70 ns

44

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~PD4264805,4265805

"

Pin Configurations (Marking Side)

,I

,i

~

32-pin Plastic TSOP (0) (400 mil) 32-pin Plastic SOJ (400 mil) ^I,

Vee GND Vee 10 32 GND

1101 2 1/08 1/01 2 1/08

1/02 1107 1/02 3 1/07

1/03 4 29 1/06 1/03 4 1/06

1/04 5 ^1::1:: _{'V 'V} 28 1/05 1/04 5 ^1::1:: _{'V 'V} 1/05

NC

.... cc ....

_{GND CAS NC 6}

cc •• .. ..

_{GND CAS}

Vee

"""

^{en ... 26 Vee 7 111111 en.}

WE S D>D>

25 OE WE 8 D>D>

OE

0 0 0 0

en en en en

RAS 9 CICI A12/NC^Note RAS 9

r-r-

_A12/NCNoto

en en

mm

AO 10 A11 AO 10 A11

A1 11 A10 A1 11 A10

A2 12 A9 A2 12 A9

A3 13 AS A3 13 A8

A4 14 A7 A4 14 A7

A5 15 A6 A5 15 A6

Vee 16 GND Vee 16 GND

Note A 12 ... J1PD4264805 NC ... J1PD4265805

AO to A12 Address Inputs 1/01 to 1/08 Data Inputs/Outputs

RAS Row Address Strobe

CAS Column Address Strobe

WE Write Enable

OE Output Enable

Vee Power Supply

GND Ground

NC No Connection

45

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NEe J,LPD4264805,4265805

Input/Output Pin Functions

The pP04264805, 4266805 have input pins RAS, CAS, WE, DE, AddressN

ot• 1

and input/output pins V01 to voa.

Pin name Input/

Function Output

RAS Input RAS activates the sense amplifier by latching a row address and selecting a (Row address strobe) corresponding word line.

It refreshes memory cell array of one line selected by the row address.

It also selects the following function .

• CAS

before RAS refresh

CAS CAS activates data input/output circuit by latching column address and (Column address strobe) selecting a digit line connected with the sense amplifier.

AO to AXNote 1 Address bus.

(Address inputs) Input total 23-bit of address signal, upper bits and lower bits in sequence (address multiplex method).

Therefore, one word is selected from 8,388,608-word by 8-bit memory cell array.

In actual operation, latch row address by specifying row address and activating RAS.

Then, switch the address bus to column address and activate CAS.

Each address is taken into the device when RAS and CAS are activated.

Therefore, the address input setup time (lASR, lAse) and hold time (tRAH, tCAH)

are specified for the activation of RAS and CAS.

WE Write control signal.

(Write enable) Write operation is executed by activating RAS, CAS and WE.

OE

Read control signal.

(Output enable) Read operation can be executed by activating RAS, CAS and

OE.

If WE is activated during read operation, OE is to be ineffective i" the device.

Therefore, read operation cannot be executed.

1/01 to 1/08 Input/ 8-bit data bus.

(Data inputs/outputs) Output _1/01 to 1/08 are used to input/output data.

Note1.

Part number Address inputs Upper bits Lower bits

IlPD4264805 AO-A12 13 10

IlPD4265805 AO-All 12 11

Hyper Page Mode

The hyper page mode is a kind of page mode with enhanced features. The two major features of the hyper page mode are as follows.

1. Data output time is extended.

In the hyper page mode, the output data is held to the next CAS cycle's falling edge, instead ofthe rising

edge. For this reason, valid data output time in the hyper page ~ode is extended compared with the fast

page mode (=data extend function). In the fast page mode, the data output time becomes shorter as the

CAS cycle time becomes shorter. Therefore, in the hyper page mode, the timing margin in read cycle is

lager than that of the fast page mode even if the CAS cycle time becomes shorter.

NEe

~PD4264805,4265805

Hyper Page Mode

The hyper page mode is a kind of page mode with enhanced features. The two majorfeatures ofthe hyper page mode are as follows.

1. Data output tim. i. axtended.

In the hyper page mode, the output data is held to the next CAS cycle's falling edge, instead of the rising edge. For this reason, valid data output time in the hyper page mode is extended compared with the fast page mode

(=

data extend function). In the fast page mode, the data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in the hyper page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter.

2. Th. CAS cycl. tim. in the hyper page mod. i. ahort.r than that in the fut page mod •.

In the hyper page mode, due to the data extend function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same.

Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that in the fast page mode is 40 ns.

In the hyper page mode, read (data out) and write (data in) cycles can be executed repeatedly during one RAS cycle. The hyper page mode allows both read and write operations during one cycle, but the performance is equivalent to that of the fast page mode in that case.

The following shows a part ofthe hyper page mode read cycle. Specifications to be observed are described in the next page.

Hyper Page Mod. Reed Cycl.

Address V,H- V,L-

V,H---.-"~-r"T"'T"---+----f+--+--+---f--+-+----+-+-H-L-+.,...

WE V,L-

L...L...L-L...L..J

tOEA

V,H-

---1\.

OE V,L-

tell

VOH- Hi·Z

I/O VOL- .--- _Jj!.:~_

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Cautions when using the hyper page mode

1. CAS

access should be used to operate tHPC at the MIN. value.

2.

To make I/Os to Hi-Zin read cycle, it is necessary to control

RAS, CAS,

WE, DE as follows. The effective specification depends on the state of each signal.

(1)

Both

RAS

and

CAS

are inactive (at the end of read cycle)

~:

inactive, OE: active

tOFC is effective when RAS is inactivated before

CAS

is inactivated.

tOFR is effective when

CAS

is inactivated before

RAS

is inactivated.

(2)

Both RAS and CAS are active or either

RAS

or

CAS

is active (in read cycle) WE, OE: inactive ... tOEZ is effective.

(3)

Both

RAS

and

CAS

are inactive or

RAS

is active and

CAS

is inactive (at the end of read cycle) WE, OE: active and either tRRH or tRCH must be met ... tWEZ and tWPZ are effective.

3.

In read cycle, the effective specification depends on the state of

CAS

signal when controlling data output with the OE signal.

(1) CAS:

inactive, OE: active ... tCHO is effective.

(2) CAS,

OE: active ... tOCH is effective.