FUNCTIONAL DESCRIPTION OF THE PROFILE ANALOG BOARD

FUNCTIONAL DESCRIPTION OF THE PROFILE ANALOG BOARD

<Refer to the six page schematic for reference details>

The following document has geen written with the purpose of descr i bing the c i rcu i tryon the Prof i I e Ana 109 Board in detail. It is not meant to be a troubleshooting guide, but is aimed at informing the technician of the different circuits and operat i ng parameters of the board. Th i s doc;ument shou 1 d be used wi th the Profi Ie Analog Board Tester, Apple Part

tt

890-0184, in testing and repairing any problem on the board.

In the event that it is desired to troubleshoot the board c,nt'c,ard the Pr'c,file unit itself, the board may be accessed using the following method:

Turn the Prc,file off and let it sit for a minute until the drive stops rotating. Access the Profile Analog board by turn

i

ng the Pr'c,f

i

1 e over or. its top, prc'v i di ng the top. cover is on the un it. Remove the metal cover under the ca.bi net which accesses the Analog board. Power the drive bacK up and refer to the schematic for the test points and waveforms. No harm can cc,me to the drive I,1Jhile it is ru"nning in this pos it i c,n, bu t random da ta errors wi 11 probabl y occur. I"lal<e gure that the drive cannot fall

ove~

or receive any sharp Jolt or shocK as this will damage the HDA media.

'.

PAGE ONE

The connector J2 on the left connects the Analo, board to the Contrcoller' board. The ~.ignals cCtrrling irlto the board are the (",rite da.ta <NRZvJDTA), the lOmhz write clctcl< (2F), the write pr·ecctmpen~.ation and cur'rent control ~.igrlcd

(PC:OMP-lOCUR), and the wr i te gate si gnal (WTGT). Outputs to the Controller board are the TRK 0 detection and Index pul~.e

signals corning from the HDA assembly. Power and ground inputs to the board are also shown for r~ference.

The trc-.cl< 0 signal indic~.tes ~\Ihen the head ~tepper motor assembly is at tracK

e

or the outer tracK location, while the index pulse occurs once per drive revolution. The index pulse can be monitored at test point TP-9 and used as an oscilloscope trigger for viewing the tracl< analog data at test point TP-1.

The +/- 0A and +/- 08 stepper motor con tr'ol pha.~.es pass through the board and are routed to the HDA' stepper motor: at cCtrlnec tor ,..17.

The Track

0

signal is obtained from the photosensor moun ted on the HDA stepper motor. The sensor i s t~ i pped by the rotating ar'm assembly on the motor =·haft when the head array is at the track

e

position, and the sensor output comes in the board at CCtnnector "T6. The =.igrlal is detected arid amplified by device UC30 and passed to the Controller bCtard CI.t J2 pin .2.

The Index Signal comes from the photosensor mounted under the HDA. The sensor is tripped by a small metal tab fastened to the bottom plastic cover of the drive spin motor and comes in the board at connector

,...Ta.

The signal is detected and ampl ified by device UC30 and passed to the Controller board at .J2 pin 4.

The write encoding and pre-compensation circuitry consists of devices IJC27 , 28, 29, and 30. The 10mhz write clock is divided by UC2 to create a 5mhz clocK <1F) for VCO res.et control purposes. The data and control signals are decoded by the PAL logic array UC28, and DlY 2 provides delay references of 10 and 2Dnsec for data signal precompensation.

This is done to compensate for the magnetic fluxes on the disk media trying to repel each other because of their polarity differences. If this happens, the flux reversals on the media will'all have mc.re or less

the

same dista,rlce between them, resulting in a sine wave

6~ttern

on the disK with no IF or 2F signal component margin

b~tween

flux reversals.

The signal outputs of the PAL indicate Early, On Time, or La.te data occurances as detected in the PAL data register.

Thes.€' are generated by cc.mparing the data bit pattern and

defining the three potential transition points for every flux

reversal with the write timing.

Thes~

signals then shift the

IIJrite data signal by selecting the prc.per amount of delay

(usually 20 nsec) to over-write any potential bit shift on the

media s.urface. This precompensates the data on the dis.K

surface, allowino a higher bit density without loss of

r·esc.l uti on.

PAGE TWO

On this page are the write amplifier, lAJrite current con tr'ol, head

:·e

I

ec

t, and read de tec t i on c i rcu i try. The WI'" i te da t a (WXS) is ga. ted through UC2 into the WI'" i te curren t dr i vel'"

array UC1 (t1PQ6700) and UC31 (MPQ2907). The data through UC2 lAJill be blocKed i f the IAIRTSM' write sector marK signal is tr'ue, as this is used to write blanK areas on the traek fe,r disK sector formatting identification.

The current level of the final driver transistor array is set by a.voltage reference de~.'eloped across zener CRI. This di c,de has a val ue of 1.2 to 1.25 '·.,tDC, wh i ch ~.ets the dr' i ve level of UCl to 24ma of write current C48ma peak-to-peaK).

This level is us·ed to write tr·e<.cKs 0 thrc1ugh 128, IIJhile tracKs 129 to 152 use les.s current because of the thinner media coating and :.maller dis·K radial ar'ea per' bit on the inner tr·acKs. Remember that the drive spin is a constant speed, and the head covers more area on an outer tracK than i t does an inner tracK during the same time period. In addition,

the media s.urface coating or, the disk is thinner towar'ds the center. The s·maller available area requires less current to effectively write the media than the laroer.

. ^-

To se t the lower curren t va I ue, the PCOl"lP-LOCUR' (Precompensation- Low Current) signal goes active, causing UC3 to "steal" 5ma from the write current value through the 1.?8Kohm r·es·is.tor R1B. This results in a lower head wr·ite current level of 19ma (38ma peaK-to-peaK) for the inner

tr·acKs.

The write current passes through diodes CR4 and

f 0 u I'" con n e c tor pin s ABC D , a r, d f I'" om the I'" e d ire c t 1 y

heads. If desired, a pin to pin wire-loop can be used AB or CD to mor, j tor the ac tua.l V,lr i

te

cur'ren t with a pr·c.be, a.s the pins are :.hunted vJith 22 c.hm r'esistor's h I? ~.d

mao

t

r·

i

x •

CR13 to to the at pins current to the

Signals

HS-l

and

HS-0

are decoded by 1 of 4 decoder UC4.

The output selects one of the four heads for either reading or writing by correctly biasing the center tap of the head coil.

The other headS are held in an off condition allowing only one head to be selected at a time.

The POJ..oJEROK signal is a monitc.r function of the pOt/,ler supply and irlstantl)' terminates any write signal i f the main povJer to the Profile unit is lost. The POWEROK line is drc,pped 1 CIW by the pOvJer c;:·upp 1 y i f the i ncc'ITd ng AC is I clst, cCo.using the volh.ge drop acrclC;:·s R16 to tur'n on.LlC13. This cuts clff L1el "Jhile there is c;:.till pClt/Jer out elf the c;:.upply maintairdng the s)'stem electronics. The POI,....IEROK signal ~.lc;:·o

holds the c;:.tepper mCltor, 28 contrc,ller, Co.nd t",r-i te Co.mpl ifier's off for a brief moment after initial power on. This delay action can be c;:·een by the READY lamp on the fr'ont panel 1 ighting for 1 to 1

&

1/2 seconds when Profile power is f i r s t turned on.

The I,....IRTSM' c;:.ignal is us·ed 'to "!"Jr-j te" (actually erao;:.e) the tr·Co.ck sector marks. The Profile uses 16 blanK sector. marKs per- tracK radially al igned on the disK, and this signal inhibits any write action to the head during the formatting of the thise areas on the disK.

The sector marKs are erased as 20usec long blanK spaces and the disK read logic needs a minimum of 10usec to identify the marK. I f any :·ec tClr' marK cln a tracK is wr i t ten over ~ the data in that :.ectclr io;:. effecti'Jel)' destr'oyed and cannot be u :·e d.

For read operation the forward biased diode matrix detects the differential analoC/ transitions (-X and -Y) of the selec~ed head. The other head; are b~ased so that there is no cur' r' e n t flow i n t h e C 0 i I , pre v e n tin 9 a. n y s i g n a I d e t e c t ion • P arlalc'g :.ignal trano;:.itions are extr'emely c;:mall and a. L '- ," p tin g t 0 OJ ie,,,, t h eo min

t

his d i 0 d eo net tAJ 0 r K i s imp 0 s sib 1 e •

PAGE THREE

The -X and -Y analog signals ente~ the ECL 10114 P r €:' am p I i f i Eo ~ S , w h i c h a r- e p C'IA) e ~ :. u p ply i sol ate d by R G 1 f 0 ~

noise immunity. The 10114 was sel€:'cted because of its excellent input geomet~y with very 1 ittle noise. The signals then pass through a low pass f i I te~ wh i ch is se t for 7. 5Mhz ,

~- 1 times the maximum read signal frequency of 2.5Mhz C2F).

~',fds

f i l t e r attenuates the major

er~or

element of the di'tected <:.ignal, which is the thir-d harmonic of the flux

~e~,'er·<:.al. I f viewed on a scope~ this is the "Knee" pa~t of the l.va~)efo~m t~an:.itic.n midwa)' behJeen :.ignal ·peaKs. The

<:ignal then ente~s a 592 video ampl ifie~ lIC6, lJJhich acts as the AGC CAutc.matic Gain CClnt~ol) integ~atclr and cc.ntr·oller.

The AGe 1 eve l i s deve loped by dev i ce Q3, a VCR2N j unc t i on whc.se bias level is corltr'olled by lICS, a 353 AGe detectc.~ a.nd ampl ifie~. The AGC cont~olled output of the 592 passes

th~o'Jgh an emitte~ follc.wer and buffer netwc.~K UC7 and is availa.ble fo~ mc.nito~ing pu~poses at test pcoints TPI .... nd TP2 at the bottom of the page. These a~e differential sign.ls and can be shown individually o~ compared with each other.

The ~.ignal le~els at these test points a~e s t i l l analog in form and should be around 1.5 to 2 volts peaK-to-peaK.

An;dhing c,ut~·ide of these levels i<:. indicative of a bad AGC networK and renders the data un~eadable to the system. I f the AGC is lost, the Prc.file cannot per'for'm the initial :·can function after power up.

I f this should happen, suspect anything in this networK.

Howeve~, remember that the :.ignals into the circuit are far tc·o :·mal1 to be mc.nitc'red directly. The best way to

t~oubleshoot anything in. this a~ea is, to SIIJap out the Ies in the circuit. T~oubleshooting to a bad component other than an Ie is almost impossible a.nd ,the boar'd may have to be scr·Co.pped out i f any othe~ component is at fault.

To the right of the UC8 pin 7 is a jumper used to set the AGe at a fixed level referenced to -12VDC. This is done only

in board manufacture test and the jumper should never be found i nth e f i ^Eo 1 d. Remove i t i f i n s t a I led.

PAGE FOUR

The AGC controlled analog signals enter two 10116 ECL schmitt level cir'cuits (UC9) which maKe up the zel"'o cr'Qssing detector. I f any signal dropout occurs because of poor AGC,

i t will be detected by this circuit and interpreted as data.

The upper pOI'" t i on oT the c i rcu i t se ts the ga in Tor a minimum amp1 itude symmetrical signal level. The lower circuit has a delay line in parallel which acts as a 1/4 wavelength

del ay 1 i ne thr'ough the s·um and cancel effect on the s.i gnal • In addition~ the delay 1 ine acts as a good low p,ss f i l t e r to el iminate "h~.sh". The c.utput of the OR gate

UCl0

is the detected signal pulse. This is allowed to happen only during

the "signal a1 lowed" p~riod set by the delay circuit.

The detected signal is then gated through UCi1 which outputs a low going pulse Tor every signal that is detected by the zero crossing detector circuit. The output of UC11 is developed by an RC networK cc.nsis.ting of C20, R65, and R66, which forms a 50nsec pulse for every flip-flop transition of UC11. IT the pulse width is les.s than 40nse-c, cape.cit-or C20 shc.uld be replaced to increase the time f~.ctor and corresponding pulse width.

As previously outlined, Profile uses bl.:o.nK areas· on the tr'acK for s·ector identification. These marKs indicate the 16 individlJal tracK sectors and are placed on the tracK ,J,lhen i t is initially formatted. I f any sector mark is oVer-wI"'itten 01'"

lost, that one sector cannot be read by the system and the d.:o.ta 'IJithin i t is lc.st.

Another schmitt trigger device

(Ue13)

coupled wi th a slow res·ponse time RC circuit is used to dete-ct these blank marKs arid will not detect any "no s.igrlal" ,period less than 10usec long. The input develc.ps thfi' signal across CRI8, CRI9, e.nd

CR28 with the RC circuit of C23 and R74 delaying the response

of one side of

UCI3.

This means that seC'r ca~not be detected i f any noise or off track data ha.s over' .ritt~;m tlhle Ibn~.nk d.isK area to the poirlt ~,Ihere i t is les.s th,- ", l(3u~.ec 1c)r;pgt_ The s·ectc.rs are v.,lritten in 20usec pel""ioCl during fO.r"1TIa'cting, so ,=·ome do?gr~.dation can Occur before 're sector is C'(!.m:"lI.U'f'1!:~ly lost.

The AM HOLD or ~.ddress 1T'-1ok hold ;s a function c.f the Write Sectc.r Mar'l< <:I.rld v,lr·ite G.:. .. e sigrlals on page 2. I t is used to clamp the circui t during write operations, which pre v eo n t s· the c. u t put f r' e·m i n de x i n g.,.. n y d a t a t c. the c c. n t r' 0 1 1 eo I'"

card •.

PAGE FIVE

On this page are the VCO (Voltage Controlled Oscillator) phase comparator control and data output circuits.

The rl?ad gate RDGT provides the cc·ntrol element for the cir·cuit. The VCO is reset during any "no read" conditic·n by the 1 F 51"1hz signa 1. Th i s a I l c ... JS the VCO to be tr i ggered almc.st i nstantanec.usl y by the RE>GT si gnal i n~.tead of recovering from an extreme compl iance condition. The circuit at the top c.f the page sets the time cc.nstant of the r·e~.et

signal (usually a few micrc.=.ecc.nd~.).

t...,hen the r'ead gate goe~. active i t tr'iggers the

veo.

^The

clr~uit then acts to locK the leading edge of the

veo

^{pulse lo}

tt'IE' leading edge of. the 50n~·ec ~.ignal data pulse. This is

done by phase comparing the data pulse with the

veo

pulse and generating a corresponding +/- INC or +/- DEC control signal.

Th is pu 1 se goes to the charge pump on pa.ge 6 wh i ch con tr'ol s the

veo

e.perat i ng fr·equenc)'. I t taKes abe.ut 20 read data

pul~es to properly control the VCO as the pulse train consists iata pulses at different intervals due to MFM criteria.

The- neo t effec t of the l . .JCO cc.n trol is to cc.mpensa te for .... ny .jiffer·ence between the r'ead cir'cuit timing and the ~peed

c,f the di sK. Any speed di fferenee creates an err'or in the data decoding as the data has to occur at 200nsec cycle periods. The VCO compensates for this, allowing a motor speed deviation of up to 3%.

The circuit does this by acting as a "locK", which Keeps the data. r'efererlced to the center c.f the

veo

pul se "vJi ndow".

The 1 ocK I i ne~· up the data pul ~·e in the cerlter of the wi ndOllJ felr ~tabil ity and pr'oper detection. The

veo

output and the data pul~.e can be mc.ni tored at (TP6 and TP7, r'espectively) to verify the leading edge of both signals occurring

~. i mu I tan e ou sly.

The last por·tion of the circuit is the ECl to TTL level tr'ansition networK at the bottom of the pa.ge. The detected NRZ data and clocK signals are fed to the Contr·ol1er bc'''.r·d

through connector

J2.

PAGE SIX

On this pa~e is the VCO circuit itself. The main portion of the c i rcu i t is the "chco.r·ge pump" for'med \>Ji th UC24 and the netwc.rK ar'our,d i t . The voltage level of the circuit is contr'olled by the INC -/+ co.nd DEC -/+ signals fr·c.m page 5.

The input of the network acts as a "sample and hold" circuit, setting the current level of the ouput transistors.

The OIJ tpu t passes through a low pass RC f i I ter to a buffer amp Ue25. This serves to buffer the current that sets

the vol ta.ge control level at the t'IV104 var'actor~ controll ing the \)CO fr·equency. The outplJt of the charge plJmp cCO.n be monitored at TP8.

The veo c.utput is appr·c.ximately 20t'lhz, arid is rc.uted to UC22 on pCO.ge 5. This is a divide by 4 circuit a.nd the r'esu 1 t i rig 5r"lhz s i goal is ttle 200n~.ec VCO "w i ndc.w" into wh i ch

the incoming read data is locked.

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