17.0 COMPATIBLE 10-BIT ANALOG-TO-DIGITAL

(1)

High Performance RISC CPU:

• C compiler optimized architecture/instruction set - Source code compatible with the PIC16 and

PIC17 instruction sets

• Linear program memory addressing to 32 Kbytes

• Linear data memory addressing to 1.5 Kbytes

• Up to 10 MIPs operation:

- DC - 40 MHz osc./clock input

- 4 MHz - 10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

• 8 x 8 Single Cycle Hardware Multiplier Peripheral Features:

• High current sink/source 25 mA/25 mA

• Three external interrupt pins

• Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler

• Timer1 module: 16-bit timer/counter

• Timer2 module: 8-bit timer/counter with 8-bit period register (time-base for PWM)

• Timer3 module: 16-bit timer/counter

• Secondary oscillator clock option - Timer1/Timer3

• Two Capture/Compare/PWM (CCP) modules.

CCP pins that can be configured as:

- Capture input: capture is 16-bit, max. resolution 6.25 ns (TCY/16)

- Compare is 16-bit, max. resolution 100 ns (TCY) - PWM output: PWM resolution is 1- to 10-bit,

max. PWM freq. @: 8-bit resolution = 156 kHz 10-bit resolution = 39 kHz

• Master Synchronous Serial Port (MSSP) module, Two modes of operation:

- 3-wire SPI™ (supports all 4 SPI modes) - I²C™ Master and Slave mode

Peripheral Features (Continued):

• Addressable USART module:

- Supports RS-485 and RS-232

• Parallel Slave Port (PSP) module Analog Features:

• Compatible 10-bit Analog-to-Digital Converter module (A/D) with:

- Fast sampling rate

- Conversion available during SLEEP - Linearity ≤ 1 LSb

• Programmable Low Voltage Detection (PLVD) - Supports interrupt on-Low Voltage Detection

• Programmable Brown-out Reset (BOR) Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced FLASH program memory typical

• 1,000,000 erase/write cycle Data EEPROM memory

• FLASH/Data EEPROM Retention: > 40 years

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own On-Chip RC Oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options including:

- 4X Phase Lock Loop (of primary oscillator) - Secondary Oscillator (32 kHz) clock input

• Single supply 5V In-Circuit Serial Programming™

(ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins CMOS Technology:

• Low power, high speed FLASH/EEPROM technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption:

- < 1.6 mA typical @ 5V, 4 MHz - 25 μA typical @ 3V, 32 kHz - < 0.2 μA typical standby current Device

On-Chip Program

Memory On-Chip

RAM (bytes)

Data EEPROM

(bytes) FLASH

(bytes)

# Single Word Instructions

PIC18F242 16K 8192 768 256

PIC18F252 32K 16384 1536 256

PIC18F442 16K 8192 768 256

PIC18F452 32K 16384 1536 256

28/40-pin High Performance, Enhanced FLASH

Microcontrollers with 10-Bit A/D

(2)

Pin Diagrams (Cont.’d)

RB7/PGD RB6/PGC RB5/PGM RB4 RB3/CCP2* RB2/INT2 RB1/INT1 RB0/INT0 VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 MCLR/VPP

RA0/AN0 RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

PIC18F442 PIC18F242

10 11 2 3 4 5 6 1

8 7 9

12 13

14 15

16 17 18 19 20 23 24 25 26 27 28

22 21 MCLR/VPP

RA0/AN0 RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1 RC3/SCK/SCL

RB7/PGD RB6/PGC RB5/PGM RB4 RB3/CCP2* RB2/INT2 RB1/INT1 RB0/INT0 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA

* RB3 is the alternate pin for the CCP2 pin multiplexing.

DIP

DIP, SOIC

Note: Pin compatible with 40-pin PIC16C7X devices.

PIC18F452 PIC18F252

(3)

1.0 DEVICE OVERVIEW

This document contains device specific information for the following devices:

These devices come in 28-pin and 40/44-pin packages.

The 28-pin devices do not have a Parallel Slave Port (PSP) implemented and the number of Analog-to- Digital (A/D) converter input channels is reduced to 5.

An overview of features is shown in Table 1-1.

The following two figures are device block diagrams sorted by pin count: 28-pin for Figure 1-1 and 40/44-pin for Figure 1-2. The 28-pin and 40/44-pin pinouts are listed in Table 1-2 and Table 1-3, respectively.

TABLE 1-1: DEVICE FEATURES

• PIC18F242 • PIC18F442

• PIC18F252 • PIC18F452

Features PIC18F242 PIC18F252 PIC18F442 PIC18F452

Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz

Program Memory (Bytes) 16K 32K 16K 32K

Program Memory (Instructions) 8192 16384 8192 16384

Data Memory (Bytes) 768 1536 768 1536

Data EEPROM Memory (Bytes) 256 256 256 256

Interrupt Sources 17 17 18 18

I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM Modules 2 2 2 2

Serial Communications

MSSP, Addressable

USART

MSSP, Addressable

USART

MSSP, Addressable

USART

MSSP, Addressable

USART

Parallel Communications — — PSP PSP

10-bit Analog-to-Digital Module 5 input channels 5 input channels 8 input channels 8 input channels

RESETS (and Delays)

POR, BOR, RESET Instruction,

Stack Full, Stack Underflow

(PWRT, OST)

(PWRT, OST) Programmable Low Voltage

Detect

Yes Yes Yes Yes

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions

Packages 28-pin DIP

28-pin SOIC

28-pin DIP 28-pin SOIC

40-pin DIP 44-pin PLCC 44-pin TQFP

(4)

FIGURE 1-1: PIC18F2X2 BLOCK DIAGRAM

Instruction Decode &

Control

PORTA

PORTB

PORTC

RA4/T0CKI RA5/AN4/SS/LVDIN

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2⁽¹⁾ RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.

2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).

3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent.

Addressable

CCP1 Synchronous

Timer0 Timer1 Timer2

Serial Port

RA3/AN3/VREF+ RA2/AN2/VREF- RA1/AN1 RA0/AN0

A/D Converter Data Latch

Data RAM

Address Latch

Address<12>

12⁽²⁾

BSR FSR0 FSR1 FSR2

4 12 4

PCH PCL PCLATH

8

31 Level Stack Program Counter

PRODL PRODH

8 x 8 Multiply

WREG

8 BIT OP

8 8

ALU<8>

8 Address Latch

Program Memory (up to 2 Mbytes)

Data Latch

21 21

16

8

8 8 inc/dec logic

21

8

Data Bus<8>

8

Instruction

12

3 ROM Latch

Timer3

CCP2

Bank0, F PCLATU

PCU

RA6

USART Master

8

Register Table Latch

Table Pointer

inc/dec logic Decode

RB0/INT0

RB4 RB1/INT1 RB2/INT2 RB3/CCP2⁽¹⁾ RB5/PGM RB6/PCG RB7/PGD

Data EEPROM Power-up

Timer Oscillator Start-up Timer

Power-on Reset Watchdog

Timer OSC1/CLKI

OSC2/CLKO

MCLR VDD, VSS

Brown-out Reset Timing

Generation

4X PLL T1OSCI

T1OSCO

Precision ReferenceVoltage

Low Voltage Programming In-Circuit Debugger

(5)

FIGURE 1-2: PIC18F4X2 BLOCK DIAGRAM

Power-up Timer Oscillator Start-up Timer

Power-on Reset Watchdog

Timer Instruction

Decode &

Control OSC1/CLKI

OSC2/CLKO

MCLR VDD, VSS

PORTA

PORTB

PORTC

RA4/T0CKI RA5/AN4/SS/LVDIN

RB0/INT0

RB4

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2⁽¹⁾ RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

Brown-out Reset

Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.

2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).

3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent.

Addressable CCP1

Master

Timer0 Timer1 Timer2

Serial Port

RA3/AN3/VREF+ RA2/AN2/VREF- RA1/AN1 RA0/AN0

Parallel Slave Port Timing

Generation

4X PLL

A/D Converter RB1/INT1 Data Latch

Data RAM (up to 4K address reach) Address Latch

Address<12>

12⁽²⁾

Bank0, F BSR FSR0

FSR1 FSR2

4 12 4

PCH PCL

PCLATH

8

31 Level Stack Program Counter

PRODL PRODH

8 x 8 Multiply

WREG

8 BIT OP

8 8

ALU<8>

8 Address Latch

Program Memory (up to 2 Mbytes)

Data Latch

21 21

16

8

8 8 inc/dec logic

21

8

Data Bus<8>

Table Latch 8

Instruction

12

3 ROM Latch

Timer3

PORTD

PORTE

RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS

CCP2

RB2/INT2 RB3/CCP2⁽¹⁾

T1OSCI T1OSCO

PCLATU

PCU

RA6

Precision ReferenceVoltage

Synchronous

USART Register

8 Table Pointer

inc/dec logic Decode

RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

Low Voltage Programming In-Circuit Debugger

Data EEPROM RB5/PGM RB6/PCG RB7/PGD

(6)

17.0 COMPATIBLE 10-BIT ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has five inputs for the PIC18F2X2 devices and eight for the PIC18F4X2 devices. This module has the ADCON0 and ADCON1 register definitions that are compatible with the mid-range A/D module.

The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number.

The A/D module has four registers. These registers are:

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The ADCON0 register, shown in Register 17-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 17-2, configures the functions of the port pins.

REGISTER 17-1: ADCON0 REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON

bit 7 bit 0

bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)

bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (AN0)

001 = channel 1, (AN1) 010 = channel 2, (AN2) 011 = channel 3, (AN3) 100 = channel 4, (AN4) 101 = channel 5, (AN5) 110 = channel 6, (AN6) 111 = channel 7, (AN7)

Note: The PIC18F2X2 devices do not implement the full 8 A/D channels; the unimplemented selections are reserved. Do not select any unimplemented channel.

bit 2 GO/DONE: A/D Conversion Status bit When ADON = 1:

1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is complete)

0 = A/D conversion not in progress bit 1 Unimplemented: Read as '0' bit 0 ADON: A/D On bit

1 = A/D converter module is powered up

0 = A/D converter module is shut-off and consumes no operating current Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown ADCON1

<ADCS2>

ADCON0

<ADCS1:ADCS0> Clock Conversion

0 00 FOSC/2

0 01 FOSC/8

0 10 FOSC/32

0 11 FRC (clock derived from the internal A/D RC oscillator)

1 00 FOSC/4

1 01 FOSC/16

1 10 FOSC/64

(7)

REGISTER 17-2: ADCON1 REGISTER

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.

0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.

bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)

bit 5-4 Unimplemented: Read as '0'

bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are

forced to be an analog input.

ADCON1

<ADCS2>

ADCON0

<ADCS1:ADCS0> Clock Conversion

0 00 FOSC/2

0 01 FOSC/8

0 10 FOSC/32

1 00 FOSC/4

1 01 FOSC/16

1 10 FOSC/64

A = Analog input D = Digital I/O

C/R = # of analog input channels / # of A/D voltage references PCFG

<3:0> AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ VREF- C / R

0000 A A A A A A A A VDD VSS 8 / 0

0001 A A A A VREF+ A A A AN3 VSS 7 / 1

0010 D D D A A A A A VDD VSS 5 / 0

0011 D D D A VREF+ A A A AN3 VSS 4 / 1

0100 D D D D A D A A VDD VSS 3 / 0

0101 D D D D VREF+ D A A AN3 VSS 2 / 1

011x D D D D D D D D — — 0 / 0

1000 A A A A VREF+ VREF- A A AN3 AN2 6 / 2

1001 D D A A A A A A VDD VSS 6 / 0

1010 D D A A VREF+ A A A AN3 VSS 5 / 1

1011 D D A A VREF+ VREF- A A AN3 AN2 4 / 2

1100 D D D A VREF+ VREF- A A AN3 AN2 3 / 2

1101 D D D D VREF+ VREF- A A AN3 AN2 2 / 2

1110 D D D D D D D A VDD VSS 1 / 0

1111 D D D D VREF+ VREF- D A AN3 AN2 1 / 2

(8)

either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/

VREF+ pin and RA2/AN2/VREF- pin.

The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the converter, which generates the result via successive approximation.

A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted.

Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference) or as a digital I/O.

The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/

ADRESL registers, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit, ADIF is set. The block diagram of the A/D module is shown in Figure 17-1.

FIGURE 17-1: A/D BLOCK DIAGRAM

(Input Voltage) VAIN

VREF+ Reference

Voltage

VDD

PCFG<3:0>

CHS<2:0>

AN7*

AN6*

AN5*

AN4 AN3 AN2 AN1 AN0 111

110 101 100 011 010 001 000 10-bit

Converter

VREF-

VSS

A/D

* These channels are implemented only on the PIC18F4X2 devices.

(9)

The value that is in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/

ADRESL registers will contain unknown data after a Power-on Reset.

After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 17.1.

After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:

1. Configure the A/D module:

• Configure analog pins, voltage reference and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

• Set PEIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared (interrupts disabled)

OR

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH/ADRESL);

clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.

17.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 17-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 kΩ. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started.

FIGURE 17-2: ANALOG INPUT MODEL

Note: When the conversion is started, the holding capacitor is disconnected from the input pin.

VAIN CPIN Rs ANx

5 pF

VDD VT = 0.6V

VT = 0.6V I LEAKAGE RIC ≤ 1k

Sampling Switch SS RSS

CHOLD = 120 pF

VSS

6V

Sampling Switch 5V

4V 3V 2V

5 6 7 8 9 10 11 (kΩ) VDD

± 500 nA

Legend: CPIN VT I LEAKAGE RIC SS CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC) various junctions

(10)

Equation 17-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution.

EQUATION 17-1: ACQUISITION TIME

EQUATION 17-2: A/D MINIMUM CHARGING TIME

Example 17-1 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assump- tions:

• CHOLD = 120 pF

• Rs = 2.5 kΩ

• Conversion Error ≤ 1/2 LSb

• VDD = 5V → Rss = 7 kΩ

• Temperature = 50°C (system max.)

• VHOLD = 0V @ time = 0

EXAMPLE 17-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

VHOLD = (VREF – (VREF/2048)) • (1 – e^(-Tc/C^HOLD^(R^IC^{+ R}^SS^{+ R}^S⁾⁾) or

TC = -(120 pF)(1 kΩ + RSS + RS) ln(1/2048)

TACQ = TAMP + TC + TCOFF

Temperature coefficient is only required for temperatures > 25°C.

TACQ = 2 μs + TC + [(Temp – 25°C)(0.05 μs/°C)]

TC = -CHOLD (RIC + RSS + RS) ln(1/2048)

-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883) -120 pF (10.5 kΩ) ln(0.0004883)

-1.26 μs (-7.6246) 9.61 μs

TACQ = 2 μs + 9.61 μs + [(50°C – 25°C)(0.05 μs/°C)]

11.61 μs + 1.25 μs 12.86 μs

(11)

17.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion.

The source of the A/D conversion clock is software selectable. The seven possible options for TAD are:

• 2 TOSC

• 4 TOSC

• 8 TOSC

• 16 TOSC

• 32 TOSC

• 64 TOSC

• Internal A/D module RC oscillator (2-6μs)

For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 μs.

Table 17-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.

17.3 Configuring Analog Port Pins

The ADCON1, TRISA and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs, must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits.

TABLE 17-1: TAD vs. DEVICE OPERATING FREQUENCIES

Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input.

Analog levels on a digitally configured input will not affect the conversion accuracy.

2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins) may cause the input buffer to con- sume current that is out of the device’s specification.

AD Clock Source (TAD) Maximum Device Frequency

Operation ADCS2:ADCS0 PIC18FXX2 PIC18LFXX2

2 TOSC 000 1.25 MHz 666 kHz

4 TOSC 100 2.50 MHz 1.33 MHz

8 TOSC 001 5.00 MHz 2.67 MHz

16 TOSC 101 10.00 MHz 5.33 MHz

32 TOSC 010 20.00 MHz 10.67 MHz

64 TOSC 110 40.00 MHz 21.33 MHz

RC 011 — —

(12)

17.4 A/D Conversions

Figure 17-3 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample.

That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion

(or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2 TAD wait is required before the next acquisition is started. After this 2 TAD wait, acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion.

FIGURE 17-3: A/D CONVERSION TAD CYCLES

17.4.1 A/D RESULT REGISTERS

The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16-bits wide.

The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D

Format Select bit (ADFM) controls this justification.

Figure 17-4 shows the operation of the A/D result justification. The extra bits are loaded with ’0’s. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers.

FIGURE 17-4: A/D RESULT JUSTIFICATION

Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11

Set GO bit

Holding capacitor is disconnected from analog input (typically 100 ns)

b9 b8 b7 b6 b5 b4 b3 b2

TAD9 TAD10

b1 b0

TCY - TAD

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion Starts

b0

10-bit Result

ADRESH ADRESL

0000 00

ADFM = 0

2 1 0 7 0 7

10-bit Result

ADRESH ADRESL

10-bit Result

0000 00

7 0 7 6 5 0

ADFM = 1

Right Justified Left Justified