Advanced numerical modeling applied to current prediction in ultimate CMOS devices

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prediction in ultimate CMOS devices

Fabio Goncalves Pereira

To cite this version:

Fabio Goncalves Pereira. Advanced numerical modeling applied to current prediction in ultimate

CMOS devices. Micro and nanotechnologies/Microelectronics. Université Grenoble Alpes, 2016. En-

glish. �NNT : 2016GREAT051�. �tel-01394979�

THÈSE

Pour obtenir le grade de

DOCTEUR DE LA COMMUNAUTE UNIVERSITE GRENOBLE ALPES

Spécialité : Nano Électronique et Nano Technologies

Arrêté ministériel : 7 août 2006

Présentée par

Fabio GONCALVES PEREIRA

Thèse dirigée par Marco PALA et

codirigée par Denis RIDEAU et François TRIOZON

préparée au sein du Laboratoire IMEP-LAHC, le CEA-Leti et de l’entreprise STMicroelectronics

dans l'École Doctorale « Electronique, Electrotechnique, Automatique et Traitement du Signal »

Advanced numerical modeling applied to current prediction in

ultimate CMOS devices

Thèse soutenue publiquement le 11 Juillet 2016, devant le jury composé de:

Mr. Gérard GHIBAUDO

DR, CNRS Alpes, Président

Mr. Arnaud BOURNEL

PR, Université Paris-Sud, Rapporteur Mr. Marc BESCOND

CR, CNRS Marseille Rapporteur

Mr. Raphael CLERC

CR, Université Jean Monnet Examinateur Mr. Denis RIDEAU

ING, STMicroelectronics, Co-encadrant

Mr. François TRIOZON

ING, CEA-Grenoble, Co-encadrant

Acknowledgements

First and foremost I would like to express my sincere gratitude to my advisors Marco Pala, Denis Rideau and François Triozon for their guidance and help throughout these PhD period.

I am very thankful for being under supervision of Marco Pala. He provided me with great support, being always available to discuss and to give me advices. I really appreciate his direct and efficient ways to tackle issues.

I am also deeply grateful for the opportunity to work with Denis Rideau. I thank him for the countless hours he spent with me, from the early bird coffee until late at night, working really hard on physics and coding. I gratefully acknowledge his huge effort to help me to develop as a professional and ultimately as a person.

I especially thank François Triozon for his humanity, guidance and professional correctness.

He has always been reachable, easygoing and rigorous with our beloved equations. I happily benefited much from his numerical experience and vast knowledge. He is a great source of inspiration.

Special thanks to my colleagues, managers and friends from STMicroelectronics who contributed with numerous advices and fruitful discussions: Gabriel, Clement Tavernier, Olivier Nier, Olivier Saxod, Assawer, Floria, Fred, Sebastien, Yvan, Marie-Anne, Guillaume, Pierre, Zahi, Pascal, Komi, Papa, Sylvain, Clement Sart, Benoit, Joris, Vincent, Gaspard, Roberto, Omar, Chris.

I will be forever indebted to Davide Garetto. I thank him for dedicating much of his time to help me with the programming world.

My appreciation and thanks go also to those colleagues, friends and relatives who somehow helped me along the way, from that simple smile to those life changing advices.

Many thanks to Marcio Matias Afonso and Marco Aurelio Schroeder who provided me a great research support for my MSc in CEFET-MG. I will be forever grateful.

At last, I thank Nicole for being my best half. I could not have come this far without her.

1 TCAD: Application and Physical’s Modeling Validity ... 17

1.1 TCAD in an industrial environment ... 18

1.2 TCAD modeling ... 18

1.2.1 Poisson equation ... 18

1.2.2 Continuity equation ... 18

1.2.3 Transport models ... 18

1.2.4 Density-Gradient quantization models ... 20

1.3 TCAD for 14FDSOI and 10FDSOI UTBB ... 22

1.3.1 Description of the simplified devices ... 22

1.3.2 Device dimensions and physical parameters ... 23

1.3.3 Source and Drain regions ... 24

1.3.4 Oxide and space charges ... 25

1.3.5 Extracted electrical quantities ... 25

1.3.6 Saturation regime and model comparison ... 26

1.3.7 14nFDSOI results ... 27

1.3.1 14pFDSOI results ... 32

1.3.2 Additional results for 14FDSOI ... 33

1.3.3 10nFDSOI predictions ... 38

1.3.4 10pFDSOI predictions ... 41

1.4 Conclusion ... 44

2 Nonlinear k.p Schrödinger-Poisson Equation with the Finite-Difference Method ... 47

2.1 Introduction ... 48

2.2 The UTOXPP solver ... 48

2.3 The Poisson Equation ... 49

2.3.1 The Boundary Conditions ... 52

2.3.2 Nonlinear Poisson Equation ... 54

2.3.3 Kerker Mixing ... 55

2.3.4 Predictor-Corrector Scheme ... 55

2.3.5 Initial Guess ... 56

2.3.6 Matrix System Solving ... 58

2.4 The Schrödinger Equation ... 59

2.4.1 No Confinement – Gas 3D ... 60

2.4.2 Confinement 1D – Gas 2D ... 61

2.4.3 Confinement 2D – Gas 1D ... 63

2.4.1 1.5D Poisson-Schrödinger ... 64

8

2.6.2 Algorithm n°2 ... 69

2.7 Simulation Results ... 71

2.8 Conclusion ... 75

3 Transport Models: From Classical to Quantum Drift-Diffusion ... 77

3.1 Introduction ... 78

3.2 Drift-Diffusion Model ... 79

3.2.1 Continuity Boundary Conditions ... 90

3.2.2 Self-Consistent Poisson-Continuity ... 95

3.3 Quantum Drift-Diffusion Model ... 97

3.4 Simulation Results for nFDSOI ... 100

3.5 Simulation Results for pFDSOI ... 106

3.6 Convergence Study ... 107

3.6.1 Comparison FEM vs FDM ... 107

3.7 Drift-Diffusion decoupling ... 109

3.8 Conclusion ... 110

4 Mobility Models ... 113

4.1 Introduction ... 114

4.2 Empirical Mobility Models ... 114

4.2.1 Charge-dependent Models ... 114

4.2.2 Field-dependent Models ... 116

4.2.3 Access Resistance ... 118

4.2.4 Velocity Saturation ... 119

4.3 Kubo-Greenwood Mobility Models ... 121

4.3.1 Mobility from Linearized Boltzmann Equation ... 121

4.3.2 Collision times calculation ... 122

4.3.3 Kubo-Greenwood in UTOXPP ... 123

4.4 Mobility Models study ... 125

4.4.1 Long Channel Mobility ... 126

4.4.2 Device Mobility ... 129

4.5 NEGF (Mode Space) in planar systems ... 132

4.5.1 Transverse -vector integration ... 133

4.5.2 Ballistic transport in effective mass: analytic k-points integration ... 134

4.5.3 Phonon scattering: numerical k-points integration ... 136

4.5.4 Decoupled mode-space approximation ... 137

4.6 Mobility extracted from NEGF simulations ... 139

4.7 NEGF versus QDD ... 141

4.7.3 Validity of QDD model ... 146

4.8 IMEP-Lahc NEGF solver applied to 14FDSOI ... 147

4.9 Conclusion ... 150

General Conclusion ... 151

Bibliography ... 154

Appendix A – TCAD Calibration ... 163

Appendix B – Poisson equation details ... 166

Appendix C – Newton-Raphson Method ... 170

Appendix D – Poisson Analytical Solution ... 171

Appendix E – Kerker Mixing vs Newton-Raphson ... 173

Appendix F – Matrix Parsing for Continuity ... 174

Appendix G – Generation-Recombination Model ... 179

Résumé ... 181

BC Boundary Condition

BOX Buried Oxide

BTE Boltzmann Transport Equations

CCS Crystal Coordinate System

CMOS Complementary Metal-Oxide Semiconductor

CPU Central Processing Unit

DCS Device Coordinate System

DD Drift-Diffusion

DG Density-Gradient

DIBL Drain Induced Barrier Lowering

DOS Density Of States

ECS Ellipsoid Coordinate System

EMA Effective Mass Approximation

EOT Equivalent oxide thickness

FD Fermi-Dirac

FDM Finite Difference Method

FDSOI Fully Depleted Silicon On Insulator

FEM Finite Element Method

GUI Graphical User Interface

HD Hydrodynamic

ITRS International Roadmap for Semiconductors

KG Kubo-Greenwood

KP2 2-band k.p

KP6 6-band k.p

LC Local Coulomb

LDD Lightly Doped Drains

LDOS Local Density Of States

MC Monte Carlo

MLDA Modified Local-Density Approximation

MOSFET Metal Oxide Semiconductor Field-Effect Transistor

MSMC Multi-Subband Monte Carlo

NEGF Non-Equilibrium Green’s function

PH Phonons

PHUMOB Philips Unified Model

PS Poisson-Schrödinger

QDD Quantum Drift-Diffusion

RC Remote Coulomb

SDT Source-Drain Tunnelling

SHE Spherical Harmonics Expansion

SOI Silicon On Insulator

SOR Successive Over-Relaxation

SR Surface Roughness

SRH Shockley-Read-Hall

TCAD Technology Computer-Aided Design

UTBB Ultra-Thin Body and Boxes

One of the most important device for semiconductor industry nowadays is the Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) which is hugely applied in the development of a vast number of electronic applications. The downscaling of MOSFET geometry has been a very successful process to improve the performances of Complementary Metal-Oxide Semiconductor (CMOS) devices and the International Roadmap for Semiconductors (ITRS) [ITRS], which is the guideline for the technology enhancements in MOSFET manufacture, aims at reducing risks in the advancements of the microelectronic industry. Nonetheless, the semiconductor industry has increasingly scaled device dimensions to improve performance and to reduce the cost [Moore 65] [Haensch 06]. The scaling of transistors dimensions according to scaling rules [Dennard 74] enabled the performance improvements up to the 90 nm technology node, but the continuous shrinking of MOSFET dimensions faces both physical and economical limitations [Thompson 05] [Haron 08].

Figure I.1: Evolution of the gate stack dimension with the technology node at High Power (HP) roadmap. Data extracted from IEDM/VLSI presentations.

In order to overcome the scaling limits and also match the ITRS performance requirement, several “boosters” have been explored by the semiconductor industries, such as the use of high-k dielectric gate stacks [Soussou 14], new channel materials (Ge, III-V) [Soussou 13]

[Mugny 15], stress engineering [Oudrhiri 15] [Nier 15] or alternative device structures such as Fully Depleted Silicon On Insulator (FDSOI) [Tavernier 15] [Toniutti 12] [Mistry 07] [Kuhn 10]

[Colinge 08]. Among the challenges encountered by the industry there are the control of current leakages [Weber 14], the enhancement of transport properties within the channel, and the control of variability (due to process or doping fluctuations) [Nassif 07].

In this introduction, we present the FDSOI structure whose architecture has been chosen to be explored in this work. Then, we describe some transport modeling issues and set the purpose of the thesis. Finally, the organization of the thesis is presented.

10¹ 10² 10³ 10⁴ 10⁵

10^-1 10⁰ 10¹ 10² 10³

HP MOSFETs @ IDEM/ VLSI

Tecnology Node [nm]

EOT/Tox [nm]

1990: 1 µ m

2008: 32 nm 2007: 45 nm

1975: 20 µ m

1985: 5 µ m 1980: 10 µ m

Strain

2005: 65 nm 2003: 90 nm

1995: 0.35 µ m 2000: 0.18 µ m

2001: 0.13 µ m HK/MG

2009: 28 nm TGate

FDSOI

FDSOI Structures

FDSOI technology is advantageous candidate structure for continuing the size reduction of the CMOS technology [Ferain 11] [Skotnicki 11]. STMicroelectronics, for instance, has already replaced the traditional bulk MOSFET device by FDSOI devices for their 28nm node and beyond [Planes 12].

Figure I.2: Simplified architecture of a FDSOI device.

Among its remarkable enhancements with respect to the bulk MOSFETs, FDSOI observes an improvement in:

1) electrostatic control: possibility of adjusting the threshold voltage by applying a back bias, giving flexibility to circuit designers to combine high performance and low power transistors in the same technology [Gallon 06] [Fenouillet 10] [Asenov 98] [Karatsori 15];

2) reduction of parasitic effects and current leakages due to lateral and vertical isolation when compared to junction isolation [Flandre 99] [Ernst 99] [Ernst 02];

3) decrease of short channel effects since the influence by drain field on the channel is reduced [Barral 07];

4) thin films and dielectric isolation offering higher transistor packing density and simplified processing [Kim 10];

5) SOI devices yield enhanced switching speed and reduced power consumption. The operating speed is improved as the isolated channel from substrate bias prevents the increase in threshold voltage of stacked SOI transistors [Soussou 14] [Kim 10].

Moreover, the planar FDSOI devices have a very similar architecture and fabrication process

as its silicon bulk predecessor MOSFET and therefore it simplifies, for instance, the

adaptation of the existing device simulation tools.

14

Transport modeling

Modeling is a powerful tool for engineering design and analysis which usually makes a description or analogy of a phenomena in order to visualize something not directly observed.

The definition of modeling may vary depending on the application, but the basic concept of modeling is the process of solving physical problems by appropriate simplification of reality.

Modeling usually consists in constructing a mathematical model for corresponding physical problems with appropriate assumptions and the model may take the form of differential or algebraic equations. In many engineering cases, these mathematical models cannot be solved analytically, often requiring a numerical solution. The process of modeling generally involves the development of an appropriate physical model and it typically requires careful calibration and validation against pre-existing data and/or analytical results. The term “device modeling”, for the microelectronics field, refers to a collection of physical models and methodologies describing carrier transport and other physical effects in semiconductor devices [Nier 15].

The transport models range from the so-called Drift-Diffusion (DD) approach [Roosbroeck 50], which is extensively used in industry due to its simplicity and efficiency, to complex and computationally demanding such as semi classical or quantum transport models. For instance, the Non-Equilibrium Green’s function (NEGF) formalism [Datta 00] [Niquet 14] [Poli 08] [Rogdakis 09] [Martinez 07] and the Monte Carlo (MC) method [Jacoboni 83] [Fischetti 88] [Querlioz 07] are common approaches used to solve respectively the Schrödinger and the Boltzmann transport equations (BTE) with few approximations or hypotheses. For advanced transport solvers such as NEGF, MC and Kubo-Greenwood (KG) [Rideau 13]

[Esseni 11b] [Kubo 57] [Dura 12], it is required an accurate description of the bandstructure of the semiconductor and also of the scattering mechanisms limiting the mobility.

In the first chapter the limitations and assumptions for industrial device simulation tools are

discussed.

Purpose of the thesis

In line with STMicroelectronics technology development strategies, this PhD work aims at improving the modeling for ultimate FDSOI nodes, with a particular attention to the carrier transport modeling. In this context, four steps have been done in this work:

1) evaluation of traditional TCAD tools to highlight the available capabilities and also the limitations;

2) development of an in-house simulation tool [Garetto 10] to overcome the limitations identified in 1);

3) benchmark of reference NEGF tools;

4) explore and improve TCAD modeling concepts.

To investigate these four challenges, research collaborations between industrial and academic actors have been established. Thus this PhD thesis was carried out in collaboration between STMicroelectronics, IMEP-LAHC, CEA-Leti in the frame of European and French ANR projects (Places2be, WaytoGoFast).

Organization of the thesis

The core of this document includes four chapters, organized as follows:

• Chapter 1 presents several simulations results for ultimate FDSOI devices and provides a rigorous comparison of advanced simulation approaches required to accurately model nowadays devices. Based on a set of templates representative of 14FDSOI and 10FDSOI devices, the electrical behavior will be simulated, enabling us to identify and calibrate each main physical mechanism taking place in the transport phenomena. Additionally, it is provided 14FDSOI experimental electrical data and corresponding simulation architectures to ensure the accuracy of advanced physical modelling with respect to process variations;

• Chapter 2 is devoted to the electrostatics device modeling, presenting the in-house two-dimensional UTOXPP Poisson-Schrödinger simulation tool;

• Chapter 3 aims at describing the Quantum Drift-Diffusion (QDD) transport model;

• Chapter 4 deals with the mobility features of device simulation tools.

1 TCAD: Application and Physical’s

Modeling Validity

Technology Computer-Assisted Design (TCAD) tools are widely used in industrial environments for modeling electrical characteristics of microelectronics components. This is mostly due to the fact that TCAD technology development can reduce cost and development time, but also secure technology choice [Nier 15]. Additionally, a reliable TCAD tool is required for developing predictive device and process simulation, for supporting the physics coherence and performance of highly scaled devices, for detecting operative limits and also for investigating new device concepts [Sasso 10].

The §1.2 presents the main components of a TCAD device modeling tool. §1.3 exposes numerous comparisons by means of TCAD simulations and explores several topics in its models §1.4 discusses the issues found in TCAD models and proposes a strategy to circumvent such concerns.

1.2 TCAD modeling

TCAD device modeling often describe the carrier distribution and transport inside a given device by solving the Poisson equation coupled to a Density-Gradient (DG) model and also to the Continuity equation and associated transport models. In this section we briefly discuss these approaches.

1.2.1 Poisson equation

The electrostatic solution of the system is determined by means of the Poisson equation, which is essentially based on the Gauss’s law [Maxwell 73]:

Basically, the Poisson equation establishes a relationship between the electrostatic potential and the electric charge density for a given material ( . The details about Poisson Equation are given in chapter 2.

1.2.2 Continuity equation

The carrier transport models can be written in the form of continuity equation, which describes the charge conservation:

The carrier transport models differ in the expressions used to compute the carrier current density .

1.2.3 Transport models

Among the simplest transport models, Drift-Diffusion (DD) has been widely used in industry

essentially due to the simplicity of its use and will supposedly continue to be applied in the

future, provided that the parameters needed in the simulation are accurately calibrated [Lundstrom 15]. Traditional TCAD tools makes available transport models such as Drift- Diffusion, which treats carrier transport as diffusion and drift processes. For the drift component, the carrier movement is due to an applied electric field, while for the diffusion component, the carrier displacement is due to spatial charge variation. For the DD transport model, the current density is typically computed as follows:

" !

## ##

$% &'

( where the is the carrier mobility, is the carrier charge density, is the electrostatic potential, is the Boltzmann constant, ! is the lattice temperature, " is the electron charge.

In the DD approach, the electron gas is assumed to be in thermal equilibrium with the lattice temperature. Nevertheless, nanoscale devices are usually under a strong electric field in which carriers gain energy from the field and therefore their temperature is raised and rather non-uniform along the device [Grasser 03].

Moreover, as the device size approaches the nanometer range, carrier transport becomes quasi-ballistic, and non-local effects such as velocity overshoot occur [Sasso 10]. In an attempt to capture these phenomena, more advanced transport models have been proposed, such as hydrodynamic (HD), which can also be found in TCAD solvers.

The following HD model can be found in Sdevice [Synopsys 14], based on Maxwell- Boltzmann statistics:

!

" *

" !

( !

" -. /

2

where !

is the carrier temperature and must not be confused with the lattice temperature ! , the fitting parameter *

is the thermal diffusion constant and /

is the effective mass.

Compared with DD, HD model has extra driving forces accounting for energy distribution on transport of carriers. As shown in 2 , besides the contribution due to spatial variation of electrostatic potential and contribution due to the gradient of carrier concentration, the current density has also a contribution due to the carrier temperature gradient and the spatial variation of the effective mass in hetero-structure devices. The HD model is capable of handling non-uniform temperatures and changes on effective masses along the device (Please note that in Chapter 3 we show that the quantum DD model proposed in this work also presents this capability).

Both the DD and HD models can be viewed as approximations of the Boltzmann transport

equation (BTE), which represents a rigorous approach to model carrier transport in

semiconductors. Different models taking into account higher moments of the BTE such as

Spherical Harmonics Expansion (SHE) can be found in the literature [Hong 09] [Jungemann

06] [Grasser 04], but they are not in the scope of this work.

20 Further details about pertinent transport models are given in Chapter 3. In addition, extra models accounting for mobility calculation in TCAD can be found in Chapter 4 and models accounting for Generation-Recombination can be found in the Appendix.

1.2.4 Density-Gradient quantization models

Theories of carrier transport can be divided according to whether they are microscopic or macroscopic in character [Ancona 11]. Microscopic theories deal with the individual carriers, such as wave functions, density matrices, etc. The macroscopic theories are devoted to the carrier populations. For the latter, semiconductor devices that are small enough are directly impacted by quantum mechanics effects, such as the phenomena of quantum confinement.

Quantum confinement is basically due to the impact on atomic structure as a result of direct effect of nanoscale lengths on the energy band structure [Zhao 04]. For nanostructures, quantum effects become relevant due to the ratio between the size of the device (thin film) or potential well in the case of electrical confinement and the mean free path of the carrier. The Figure 1.1 illustrates the classical distribution and the quantum confinement in a nanoscale device:

Figure 1.1: Classical and Quantum charge density profiles showing the quantum confinement effect. Si thickness of 6nm.

Contrary to classical charge distribution, the quantum confinement is described by envelop functions associated to a well-defined number of discrete energy levels and these envelop functions will have their maximum density pushed-away from the Si-SiO

interface. The low- density zone close to this interface is the so-called “dark space”. For a quantum confinement in the channel thickness direction, electrons are no longer represented as a 3D electron gas (3DEG), but as a 2D electron gas (2DEG) in which the transport is modeled in the two dimensions of the channel plan (further details will be presented in section 2.4).

A simplified TCAD model accounting for quantization effects is given, for instance, by the modified local-density approximation (MLDA) which is a model that calculates the confined carrier distributions occurring near semiconductor-insulator interfaces [Synopsys 14] [Paasch 82]. It can be applied to both inversion and accumulation regimes, and simultaneously to

POSITION

CHARGE DENSITY

CLASSICAL

QUANTUM CONFINEMENT

Si

SiO2 SiO2

electrons and holes. The confined electron density at a distance 3 from a Si-SiO

interface is given for the Maxwell-Boltzmann distribution by:

4 3 5

789 :

789 3<=

?

where 5

is the electron density of states, :

@

@

< ! in which @

is the quasi- Fermi level and @

is the conduction band. =

BC

< /

! is the electron thermal wavelength which depends on the quantization mass /

.

Another model for accounting for quantum confinement effects used in TCAD tools in ultra- scaled devices is the Density-Gradient (DG) model. This model is described in E [Ancona 87] [Ancona 89] and implemented in Sdevice as:

4 5

F

H @

@

I

J !

K E

where the F

is the Fermi-Dirac statistics and I

is the quantum potential given by:

I

LC

E/

>

O4

O4 P

where L is a fitting parameter “weighting factor” for quantum potential (this L must not be confused with the “quantum statistics correction factor” which will be presented in chapter 3).

The expressions E and P are for electrons and similar equations are applied to holes.

Furthermore, rather more elaborated models must be applied in order to account for extra features such as stress, non-parabolic bands and geometric quantization in thin-layer structures [Penzin 11], and for all these models appropriated calibrations are needed.

Figure 1.2 illustrates an example of calibration adjustment done for a Density-Gradient model:

Figure 1.2: Example for pMOS 14FDSOI structure with DG with (Q R S) and without (Q T) calibration compared to reference k.p 6-bands in [100] direction. Classical and Quantum charge density profile for VG=-0.9V (applied on l.h.s) with VDS=VB=0V.

Si film position is from 2.8nm to 8.8nm.

The calculation of the electron concentration in the presence of confinement effect requires to solve, for instance, the Poisson and Schrodinger equation self-consistently [Colinge 06].

However, when DG is required, one can also make use of the self-consistent Poisson- Schrödinger solution for a proper calibration of the model [Pons 13].

1 2 3 4 5 6 7 8 9 10

0 1 2 3 4x 10²⁵

X POSITION [nm]

CHARGE DENSITY [/M3]

CLASSICAL

POISSON-SCHRODINGER(REF) DENSITY-GRADIENT(UNCALIBRATED) DENSITY-GRADIENT(CALIBRATED)

SiO2 Si

22 In this chapter, it will be examined the consistency of traditional TCAD tools for modeling ultimate devices in which all simulations are performed with DG along its analysis of validity and limitations.

1.3 TCAD for 14FDSOI and 10FDSOI UTBB

TCAD for industrial purposes is based on an accurate modeling of the process steps.

However, since this work is focused on the device itself, simplified 14FDSOI and 10FDSOI devices with ultra-thin body and boxes (UTBB) have been created. These template devices have been carefully set up in order to match the characteristics of process-simulated devices as it will be shown later in this work. The process variations such as Lightly Doped Drain (LDD) extension change and morphological variations are mimicked using analytical functions and parameterized structures.

In this Chapter, we will presented comparisons by means of simulations performed with Sdevice [Synopsys 14] using Density Gradient model with either DD or HD transport model.

For both models, the same channel-thickness dependent mobility, the remote Coulomb scattering and the nonlinear piezoelectric strain-dependent models are used. The details on these models and the calibration procedures on advanced solvers can be found in [Nier 13].

1.3.1 Description of the simplified devices

In order to proceed with the modeling investigation, the template device architecture is shown in Figure 1.3 for both nMOS and pMOS:

Figure 1.3: Description of FDSOI (nMOS and pMOS).

The gate stack is composed by High-k material ( UVW

, X ) over the Interfacial layer-IL

( YZ[5\ X E E ). The spacer is composed by a Nitride ( ]^

`

, X P ? ). The Buried Oxide

(Box) is composed by Silicon oxide ( ]^W

, X ( b ). The ground plane is composed by Silicon

( ]^ , X P ) with Boron doping concentration 8

d/

for the nMOS and Phosphorus

doping concentration 8

d/

for the pMOS. The source and drain regions of nMOS device are composed by Silicon ( ]^ , X P ) with Phosphorus doping concentration (f

d/

. The pMOS device features SiGe epitaxied in-situ doped Source/Drain with Boron doping concentration of (f

d/

. The SOI <110>-oriented channel has a Boron doping concentration ?8

d/

for all cases. The lattice temperature for all simulations in this work is set to 300K.

In 14FDSOI and 10FDSOI technologies, nMOS channels are composed by Silicon and pMOS are composed by SiGe varying the Ge content as follows:

nMOS pMOS

10FDSOI 14FDSOI 10FDSOI 14FDSOI

%Ge %Ge %Ge %Ge

0 0 30 / 45 30

Table 1.1: Left: nMOS Ge content. Right: pMOS Ge content. The highlighted values indicate the references.

Additionally, a mechanical stress booster is implemented in order to further increase the longitudinal component of the stress for both 10FDSOI and 14FDSOI, as indicated in Table 1.2:

nMOS pMOS

Ltot(nm) Sw(GPa) Sch (GPa) Sw (GPa) Sch (GPa)

14FDSOI 0 0 0 -2.3

10FDSOI 0 2 0 -2.6

Table 1.2: Stress for different technologies.

where Sw and Sch stand for the stress, respectively, along the transverse and transport directions.

1.3.2 Device dimensions and physical parameters

The dimensions for the proposed FDSOI devices (nMOS and pMOS) are indicated in Figure 1.4:

Figure 1.4: Definition of the dimensions.

24

14FDSOI nMOS pMOS

Ltot(nm) 74 (for Lg =24 nm) 74 (for Lg =24 nm)

Lg (nm) 24; 28; 34; 64; 104; 304; 1004 24; 28; 34; 64; 104; 304; 1004

Tsi(nm) 6 6

Width( m) 1 1

Lsp(nm) 6 (Nitride ε=7.5) 6 (ε=7.5)

TOX(nm) 1 (SiON ε=6.6) 1 (ε=6.6)

THK(nm) 1.8 (HfO2 ε=20) 1.8 (ε=20)

Tbox (nm) 20 (SIO2ε=3.9) 20 (ε=3.9)

Lext(nm) 4.5 4.5

Ls(nm) 27 27

QIL (f ^G_d/^e> (f ^G_d/^e>

Work Function 4.8eV 5.132eV

Racc(Ohms) 2x50 2x20

Stress (GPa) none Sch =-2.3 (uniaxial compressive

along the channel direction)

XGe 0% 30%

Spacer charge Qss 0 0

h for Density Gradient 4.0 7.9

Table 1.3: Device specifications for 14FDSOI (nMOS and pMOS). The bold values are the references, and process variations ranges are indicated.

Assuming that the Ltot=74nm for Lg=24nm, we consider 50nm of S/D region to ensure consistent boundary conditions of the simulations. Lext=4.5nm is given value accounting for source/drain epitaxy and silicidation process. Note that the reference values (in bold) are corresponding to the ones used for the comparison of TCAD results and electrical measurements.

1.3.3 Source and Drain regions

The LDD region has potentially different doping profiles. In order to provide an example of a process variation, we consider a split of the spacer thickness and final anneal temperature split (i.e. the diffusion of the in-situ doped S/D region). Doping profiles obtained from process simulations can be either fitted by a Gaussian or by an analytical expression.

Figure 1.5: Description of FDSOI doping profiles by means of analytical functions. The film doping profile along the transport direction varies from n-doped ijklmn^ei in source and drain

sides to p-doped ojpomn^ei in the middle of channel.

This has been emulated changing the doping profile parameters q ^and r :

* 8 (7 d/

s

t

w s

H

K y

where 8 is the position along the channel while all other device reference parameters are kept identical. The chosen parameter values for q ^and r are shown in Table 1.4:

q r

LDD 1 parameters 21 15 LDD 2 parameters 25 15

Table 1.4: LDD parameters (a) and (b). The highlighted values are references.

1.3.4 Oxide and space charges

The charge between the High-K and Interfacial layer give rise to remote Coulomb scattering and can be simulated for typical values of Q

= d/

, (8

d/

and , ? 8

d/

as follows:

Figure 1.6: Charge located between High-K and Interfacial layer.

Associated to the charge variation a change of the gate work function (WF) has to be accounted for to avoid a shift of the threshold voltage (V

). The proposed couples (Q

/WF) are provided in the following table.

1XFDSOI 14nMOS pMOS (sSi) pMOS (sSiGe 30%)

QIL = d/^{e> 4.385eV - -}

(8 ^G_d/^{e> 4.8eV 5.292eV 5.132eV}

? 8 ^G_d/^{e> 5.125eV - -}

Table 4: Interfacial charges and respective gate work functions.

Finally a charge between the spacer region and the silicon layer can exist as shown in Figure 1.7 and simulations can be performed for Q

= d/

and (f

d/

.

Figure 1.7: Charge located between spacer region and the silicon layer.

1.3.5 Extracted electrical quantities

Rather than reporting directly I

-V

curves, it is preferable to show more industrial-oriented

figures of merit in the next sections. The most important extracted electrical quantities are the

26 V

=0V). This defines the ratio between the maximum “drive” current and the off state leakage. Besides, the V

values (for both linear and saturation regimes) are used to control the centering of the transistors and the control of the Drain Induced Barrier Lowering (DIBL).

Among all possible V

extraction methods, we propose to use the V

at constant current (I

=300e-9/L(µm) for nMOS and I

=70e-9/L(µm) for pMOS) as illustrated in Figure 1.8.

Another important electrical quantity that can be extracted is the linear current at constant overdrive I

Lin. The overdrive is defined as V

-V

= V

=0.3V and 0.5V, and the Drain is biased in the linear regime (hereafter we propose V

lin= 0.05V). I

Lin is a valuable figure of merit for the calibration of the mobility and the access resistance. The I

Lin can be shown as a function of the DIBL (difference between V

sat and V

lin) or as a function of I

. The ratio I

Lin /I

for strain engineering can be interesting since it quantifies the mobility gain versus the maximum “drive” current gain. The principle of the extractions is shown in Figure 1.8:

Figure 1.8: Principle of the extracted figures of merit from simulated ID-VG curves. For this example the reference 14nFDSOI device has been used. Currents simulated at VD=0.05V(linear

regime) and 0.9V(saturation regime).

1.3.6 Saturation regime and model comparison

In general a good agreement between DD (or HD) models and experimental data is obtained in the linear regime. However, as shown hereafter, the simulated results in the saturation regime can strongly depend on the chosen transport model. This is partly due to the transport equation solved themselves (DD or HD), but it is also due to a more fundamental root cause: the concept of velocity saturation occurring at high field.

In typical DD and HD models the high-field saturation modeling consists in two submodels acting on the low field mobility model: the velocity saturation model, and the driving force model. Concerning the velocity saturation model, we used the so called Canali Model [Canali 75] in order to compute the high-field mobility:

0 0.2 0.4 0.6 0.8 1

10^-8 10^-7 10^-6 10^-5 10^-4 10^-3 10^-2

VG (V)

CURRENT (A)

VGmax IRef = 300e-9/0.024

= 1.25e^-5

VTHsat VTHlin

Ioff

Isat

L=0.024 µ ^m

IoDLin (V

GT = 0.5 V)

z

~ t

z

•

w

ƒ

^b

where

denotes the low-field mobility and its value depends on the chosen mobility model (e.g. the value of

for the Philips Unified model [Klaassen 92] for electrons = 52.2cm

/V/s). The values of the velocity saturation V

and of the exponent „ are generally chosen in order to reproduce measurements in bulk silicon: V

= 1.07e07cm/s, 8.37e06cm/s and „ = 1.40, 0.93 for electrons and holes, respectively. However, in a realistic short-channel device, the driving electric field is no longer constant along the current path and the velocity saturation concept becomes somehow irrelevant due to e.g. to velocity overshoot phenomena [Hiblot 15]. The saturation regime of MOSFETs devices is a real concern for standard TCAD simulations. In practice, the best “local” driving force to be used in a device simulation remains unclear.

In what follows, we have chosen to use the gradient of the quasi-Fermi level for DD simulations and the carrier temperature for the HD model. These two transport models are the default models suggested by TCAD Sdevice by Synopsys [Synopsys 14].

However, Sdevice makes use of ambiguous “driving forces” in its models (e.g. DD with gradient of the quasi-Fermi level as a driving force and HD with carrier temperature as a driving force). As for the FDSOI modeling, TCAD tools can be significantly doubtful for correctly evaluate the below-spacer region and also when evaluating simulations under large back bias conditions [Pereira 15]. In addition, these tools have been challenged on many aspects for modeling ultimate technologies such as single high permittivity dielectric and metal gate stack with dual channel material.

In this chapter we show that the fundamental limits of the DD and HD models can be emphasized when two models, well calibrated on a given device (in what follows on the 14FDSOI characteristics), predict qualitatively different characteristics on another device (e.g. 10FDSOI). Similarly, the sensitivity of the current as a function of the geometry variations appears to significantly depend on the chosen model.

1.3.7 14nFDSOI results

The simulated devices in this section correspond to the 14FDSOI reference template device

described by Figure 1.3 and Figure 1.4, with reference LDD (a=21; b=15), Q

= ? f

d/

,

Q

= d/

and R

= 8 ? …†/‡ . Figure 1.9 shows the I

– I

characteristic for the

14nFDSOI devices in which DD and HD models are compared and the measurements are

averaged on a large number of identical devices and correspond to devices that pertain to

technologies at different stages of development maturity.

28

Figure 1.9: Ioff – Ion in 14 FDSOI (nMOS) for different transport models. Symbols are measurements and lines are simulations for different values of access resistance (Racc) and

velocity saturation (Vsat).

In Figure 1.9, the DD model is compared to HD model by significantly varying in the latter, once a time, either the V

or the R

in order to match the HD I

currents. These variations (for HD model only) are also observed in Figure 1.10 with a R

increasing up to 8 P …†/‡ (keeping the default bulk value for V

=1.07e7cm/s) in order to match the I

currents:

Figure 1.10: Ioff – Ion in 14 FDSOI (nMOS) and ‘pragmatic’ adjustments of the HD model predictions. Symbols are measurements and lines are simulations for different access

resistance (Racc) and velocity saturation (Vsat).

It is acknowledged that these two adjustments observed in Figure 1.10 are unphysical, but it has been done for pragmatic reasons.

It should also be mentioned that the linear current predicted by the HD model with R

= 8 P …†/‡ is much lower than the predictions of the two other models (DD and HD), but also the measurement values.

0 200 400 600 800 1000 1200

10^-12 10^-10 10^-8 10^-6

Isat [uA/um]

Ioff [A/um]

14FD Exp (early hardware) 14FD Exp (optimized hardware) DD: 50ohm-Vsat1.07e7 HD: 50ohm-Vsat0.5e7 HD: 170ohm-Vsat1.07e7

0 200 400 600 800 1000 1200 1400 1600 1800

10^-12 10^-10 10^-8 10^-6

Isat [uA/um]

Ioff [A/um]

HD: 50 Ohm/ Vsat 1e7

14FD : optimized hardware HD: 50 Ohm/ Vsat 5e6

HD: 170 Ohm/ Vsat 1e7

HD: 50 Ohm/ Vsat 6e6

Therefore, the HD solution might not be worth to be further explored and the DD (with driving force as “gradient of quasi-Fermi level”) should be hereafter considered as reference.

1.3.7.1 Increase of the spacer thickness.

In order to provide an example of a process variation, different values of the spacer thickness (an increase of the spacer deposit of 4nm) are simulated by changing the doping profile parameters as mentioned in the Table 3. All other device template parameters are kept identical. Figure 1.11 shows the I

-I

corresponding to the technological split:

Figure 1.11: Ioff – Ionin 14 FDSOI (nMOS) for two technological splits consisting in increasing the spacer thickness by 4nm (i.e. shifting the S/D doping profile by 4nm). TCAD with DD (Racc=2x50Ohms / Vsat=1.07e7cm/s) but also with HD (Racc=2x50Ohms/ Vsat=0.5e7cm/s). Symbols are the measurements data.

Both simulations and measurements are overlaid and a satisfactory match is achieved with DD (R

= 8 ? …†/‡ and V

=1.07e7cm/s) but also with HD (R

= 8 ? …†/‡ and V

=0.5e7cm/s).

Associated with the change in the LDD region, the threshold voltage (and the DIBL) changes for different device lengths as depicted in Figure 1.12. TCAD results are also shown to demonstrate that the electrostatics is correctly reproduced (HD model satisfactory match DD model and are not shown).

100 200 300 400 500 600 700 800 900

10^-10 10^-8

Isat [uA/um]

Ioff [A/um]

DD HD LDD1 LDD2

30

Figure 1.12: VTH vs L in 14 FDSOI (nMOS) for two technological splits consisting in increasing the spacer thickness by 4nm (i.e. shifting the S/D doping profile by 4nm). TCAD with DD (Racc=2x50 Ohms/ Vsat=1.07e7cm/s). Symbols are the measurements data.

Concerning the linear regime (and thus related to the mobility), Figure 1.13 shows the I

Lin as a function of I

. Some differences can be seen with DD and HD, but it is not clear which model reproduces the measurement data more accurately.

Figure 1.13: IoDLin vs Isat in 14FDSOI (nMOS) for two technological splits consisting in increasing the spacer thickness by 4nm (i.e. shifting the S/D doping profile by 4nm). TCAD with DD (Racc=2x50 Ohms/

Vsat=1.07e7cm/s) but also with HD (Racc=2x50 Ohms/ Vsat=0.5e7cm/s). Symbols are reference measurements.

Figure 1.14 shows the I

lin vs DIBL for the two splits and Figure 1.15 shows the DIBL vs I

(for sake of clarity, only DD model predictions are shown):

10^-1 0.2

0.22 0.24 0.26 0.28 0.3 0.32 0.34 0.36

L [µm]

VTlin, VTsat (V)

Exp: LDD2 Exp: LDD1 TCAD: LDD2 TCAD: LDD1

Saturation Linear

0 100 200 300 400 500 600 700 800 900 1000

0 50 100 150 200

Isat (uA/um)

Iodlin (uA/um)

Ref: LDD1 Ref: LDD2 TCAD: LDD1-DD TCAD: LDD2-DD TCAD: LDD1-HD TCAD: LDD2-HD

Iodlin 0.3 Iodlin 0.5

Figure 1.14: IoDLin vs DIBL in 14 FDSOI (nMOS) for two technological splits consisting in increasing the spacer thickness by 4nm (i.e. shifting the S/D doping profile by 4nm). TCAD with DD (Racc=2x50 Ohms/

Vsat=1.07e7cm/s). Symbols are reference measurements.

Figure 1.15: DIBL vs Isat in 14 FDSOI (nMOS) for two technological splits consisting in increasing the spacer thickness by 4nm (i.e. shifting the S/D doping profile by 4nm). TCAD with DD (Racc=2x50 Ohms/

Vsat=1.07e7cm/s). Symbols are reference measurements.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0

50 100 150 200

DIBL [V/V]

Iodlin [uA/um]

Exp: LDD1 Exp: LDD2 TCAD: LDD1 TCAD: LDD2 Iodlin 0.5

Iodlin 0.3

0 100 200 300 400 500 600 700 800 900

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09

Isat (uA/um)

DIBL [mV/V]

Ref: LDD2 Ref: LDD1 TCAD: LDD2 TCAD: LDD1

32

1.3.1 14pFDSOI results

Figure 1.16 shows the I

– I

characteristic for the 14pFDSOI devices. As for the 14nFDSOI, the simulated devices correspond to the reference template described by Figure 1.3 and Figure 1.4 with reference LDD1 (a=21; b=15), Q

= (f

d/

, Q

= d/

and R

= f …†/‡ . DD and HD models are compared (keeping the default bulk value for V

=0.83e7cm/s)

Figure 1.16: Ioff – Ion in 14pFDSOI for various transport models. TCAD with DD (Racc=2x20 Ohms and Vsat=0.83e7cm/s) but also with HD (Racc=2x20 ohms and Vsat=0.83e7cm/s). Symbols are measurements.

The threshold voltage as a function of the gate length is shown in Figure 1.17:

Figure 1.17: Experimental VTH versus L in 14pFDSOI and TCAD with DD (Racc=2x20 Ohms and Vsat=0.83e7cm/s).

Figure 1.18 shows the I

Lin vs I

:

-1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 10^-14

10^-12 10^-10 10^-8 10^-6

Isat [uA/um]

Ioff [A/um]

14FD Exp (early hardware) 14FD Exp (Optimized hardware) DD: 20ohm-Vsat0.83e7 HD: 20ohm-Vsat0.83e7

10^-2 10^-1 10⁰

-0.4 -0.35 -0.3 -0.25 -0.2 -0.15

L (um)

THRESHOLD VOLTGAE (V)

EXP (early hardware) TCAD: Lin

TCAD: Sat

Figure 1.18: Experimental IoDLin versus Isat in 14pFDSOI and TCAD with DD (Racc=2x20 Ohms and Vsat=0.83e7cm/s) but also with HD (Racc=2x20 Ohms and Vsat=0.83e7cm/s).

1.3.2 Additional results for 14FDSOI

In order to further investigate the available modeling simulation tools, it is also performed simulations by varying the channel material and stress impact on 14pFDSOI devices.

Moreover, the LDD split for 14nFDSOI is also simulated.

1.3.2.1 Germanium Impact on 14pFDSOI

Let us now compare a strained-Silicon channel versus a strained-SiGe channel in 14pFDSOI. The Work Function (WF=5.292 in Si and WF=5.132 in SiGe 30%) is changed in order to match the threshold voltage for the shortest device. For this device, the threshold voltage (and consequently the DIBL) as a function of the gate length is depicted in Figure 1.19:

Figure 1.19: VTH vs L in 14pFDSOI obtained from TCAD with DD (Racc=2x20 Ohms/ Vsat=0.83e7). The thick lines correspond to uniaxial strained SiGe (Sxx=-2.3GPa, XGe=30%) and the thin lines to uniaxial strained Silicon (Sxx=-2.3GPa). Linear regime at VD=0.05V and saturation regime at VD=0.9V.

-1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 -200

-150 -100 -50 0

Isat (uA/um)

Iodlin (uA/um)

EXP (early hardware) TCAD: DD

TCAD: HD Iodlin 0.5 Iodlin 0.3

10^-2 10^-1 10⁰

-0.4 -0.35 -0.3 -0.25 -0.2 -0.15

L (um)

VTlin, VTsat (V)

VTsat

VTlin

34 It is important to mention that in both regimes, the strain is kept identical and only the Ge fraction is changed (impacting the band gap, the permittivity and the electronic affinity).

The Figure 1.20 shows the I

-I

for the 14pFDSOI:

Figure 1.20: Ioff – Ion in 14 FDSOI (pMOS) for various transport models. TCAD with DD (Racc=2x20 Ohms/

Vsat=0.83e7) but also with HD (Racc=2x20 Ohms/ Vsat=0.83e7). The thick lines correspond to uniaxial strained SiGe (Sxx=-2.3GPa, XGe=30%) and the thin lines to uniaxial strained Silicon (Sxx=-2.3GPa).

As can be noted in the threshold voltage shown in Figure 1.19, the short channel effect are slightly more pronounced in the SiGe device due to a larger dielectric constant ( X P in Si and X E in Ge). However, the I

-I

trends are similar as testified by Figure 1.20.

Moreover, the I

lin as a function of I

is shown in Figure 1.21:

Figure 1.21: IoDlin vs Isat in 14 FDSOI (pMOS) obtained using TCAD with DD (Racc=2*20 Ohms/

Vsat=0.83e7cm/s) but also with HD (Racc=2*20 Ohms/ Vsat=0.83e7cm/s). The thick lines correspond to uniaxial strained SiGe (Sxx=-2.3GPa, XGe=30%) and the thin lines to uniaxial strained Silicon (Sxx=- 2.3GPa).

It should be noted that the piezoelectric model used in these simulations does not account for the Ge content, which implies that the I

lin is not impacted by the Ge content as shown in Figure 1.21, and this is an intrinsic limitation of our TCAD platform when the impact of Ge has to be accounted for.

-1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0

10^-13 10^-12 10^-11 10^-10 10^-9 10^-8 10^-7

Isat [uA/um]

Ioff [A/um]

14FD Exp (early hardware) 14FD Exp (Optimized hardware) DD: 20ohm-Vsat0.83e7 HD: 20ohm-Vsat0.83e7

-1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 -160

-140 -120 -100 -80 -60 -40 -20 0

Isat (uA/um)

Iodlin (uA/um)

TCAD: DD TCAD: HD Iodlin 0.5 Iodlin 0.3

1.3.2.2 Stress Impact on 14pFDSOI

In this subsection, unstrained-SiGe 14pFDSOI are compared with strained-SiGe 14pFDSOI.

One should notice that the comparison is made by only changing the strain (impacting the mobility and the band gap) and keeping the other quantities and dimensions unchanged. As a consequence, the threshold voltage shown in Figure 1.22 is shifted by about 50 mV due to strain-induced-bandstructure change.

Figure 1.22: VTH versus L in 14FDSOI (pMOS) for the strained Si (Sxx=-2.3GPa) and also for the unstrained Si (Sxx=0GPa). TCAD with DD (Racc=2 x 20 Ohms and Vsat=0.83e7cm/s).

I

– I

and I

lin versus I

are shown in Figure 1.23 and Figure 1.24 respectively. The benefit of uniaxial compressive stress on the device performance is clearly visible in the figures. A large difference for the gain in the saturation regime calculated with DD and HD is observed. Such uncertainties emphasize the limitation of “standard” and supposedly calibrated DD and HD in TCAD approaches.

.

Figure 1.23: Ioff – Ion in 14 FDSOI (pMOS) for the strained Si (Sxx=-2.3GPa) and also for the unstrained Si

10^-2 10^-1 10⁰

-0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1

L [µ^m]

VTlin, VTsat (V)

14FD VTsat Sxx=-2.3Gpa 14FD VTlin Sxx=-2.3Gpa 14FD VTsat Sxx=0Gpa 14FD VTlin Sxx=0Gpa

VTsat: Sxx=-2.3GPa

VTlin: Sxx=0GPa

VTsat: Sxx=0GPa VTlin: Sxx=-2.3GPa

-1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 -10^-6

-10^-8 -10^-10 -10^-12 -10^-14

Isat [uA/um]

Ioff [A/um]

DD: 14FD Sxx=-2.3GPa DD: 14FD Sxx=0GPa HD: 14FD Sxx=-2.3GPa HD: 14FD Sxx=0GPa

HD: -2.3GPa

DD: -2.3GPa

DD: 0GPa

HD: 0GPa

36 Figure 1.24 shows the I

lin versus I

:

Figure 1.24: IoDLin vs Isat in 14FDSOI (pMOS) for the strained Si (Sxx=-2.3GPa) and also for the unstrained Si (Sxx=0GPa). TCAD with DD (Racc=2*20 Ohms/ Vsat=0.83e7) but also with HD (Racc=2*20 Ohms/

Vsat=0.83e7). IoDLin at VGT=0.3V.

As previous observed, the Figure 1.24 also displays the undesirable mismatch between DD and HD models.

1.3.2.3 LDD split with DD on 14nFDSOI

Some brief additional studies have been done to study on the impact on LDD profiles. This impact using the set of parameters q ^and r reported in Table 3 and depicted in Figure 1.5 is twofold: firstly, the parameter q mimics a change in the space thickness since it “moves” the dopants profile along the channel; secondly, the parameter r mimics the diffusion of the in- situ doped S/D since it acts like a “cuttoff’” of the profile extension in the channel.

Figure 1.25: Doping profile for various LDD parameters (a,b) provided in the legend.

Figure 1.26 and Figure 1.27 show, respectively, the I

Lin (V

=0.3V) – DIBL and I

– I

(V

=0.9V) for various doping parameters:

-1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 -100

-80 -60 -40 -20 0

Isat (uA/um)

Iodlin (uA/um)

DD: 14FD Sxx=-2.3GPa DD: 14FD Sxx=0GPa HD: 14FD Sxx=-2.3GPa HD: 14FD Sxx=0GPa

HD: 0GPa DD: 0GPa

DD: -2.3GPa HD: -2.3GPa

-0.03 -0.02 -0.01 0 0.01 0.02 0.03

10¹⁶ 10¹⁸ 10²⁰

POSITION (µ ^m)

DOPING (cm-3 ) 21,15

21,20 21,5 17,15 17,20 17,5 25,15 25,20 25,5