IN SITU PROCESSING OF InP BY FLASH LPCVD FOR SURFACE PREPARATION AND GATE OXIDE DEPOSITION

(1)

HAL Id: jpa-00227942

https://hal.archives-ouvertes.fr/jpa-00227942

Submitted on 1 Jan 1988

HAL

is a multi-disciplinary open access archive for the deposit and dissemination of sci- entific research documents, whether they are pub- lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers.

L’archive ouverte pluridisciplinaire

HAL, est

destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

IN SITU PROCESSING OF InP BY FLASH LPCVD FOR SURFACE PREPARATION AND GATE OXIDE

DEPOSITION

Y. Nissim, C. Licoppe, J. Moison, C. Meriadec

To cite this version:

Y. Nissim, C. Licoppe, J. Moison, C. Meriadec. IN SITU PROCESSING OF InP BY FLASH LPCVD

FOR SURFACE PREPARATION AND GATE OXIDE DEPOSITION. Journal de Physique Collo-

ques, 1988, 49 (C4), pp.C4-213-C4-215. �10.1051/jphyscol:1988444�. �jpa-00227942�

(2)

JOURNAL DE PHYSIQUE

Colloque C4, suppldment au n09, Tome 49, septembre 1988

IN SITU PROCESSING OF InP BY FLASH LPCVD FOR SURFACE PREPARATION AND GATE OXIDE DEPOSITION

Y.I. NISSIM, C. LICOPPE, J.M. MOISON and C. MERIADEC

CNET, L a b o r a t o i r e d e B a g n e u x , 1 9 6 , Av. H. Ravera, F-92220 B a g n e u x , F r a n c e

RGsunE

-

Des films de s i l i c e sont rCalisEs dans un rgacteur CVD operant 'a basse pres- m r e f r o i d i par a i r e t eau e t command6 par chauffage optique rapide. Des v i t e s s e s

de depdt a l l a n t jusqu'a 100 u/sec sont obtenues sous un flash thermique de 700°C. Ces dGpdts sont effectues sur InP sans que sa surface s o i t endomnagGe. Les stuctures InP/SiO ainsi forme'es ont d'excellentes proprietes Glectriques adaptees aux exigences du M I S ~ T . ~ ' a l l i o r a t i o n des propriGt6s d ' i n t e r f a c e de c e t t e s t r u c t u r e e s t obtenue par exposition de l a surface d'InP au s i l a n e avant l e depdt d'oxide. Une gtude de surface indique que l e s i l a n e reduit l e s oxydes n a t i f s d'InP.

Abstract

-

Silicon dioxide films deposited on InP substrates a r e obtained in a reduced pressure, a i r and water cooled CVD reactor, w i t h a rapid thermal heating. I t i s shown t h a t a 700°C temperature flash r e s u l t s i n SiO deposition r a t e s close t o 100 hjsec.

High temperature deposition (700°C) is thus obzained i n few seconds on InP substrates without any surface damage. These layers display excel l e n t e l e c t r i c a l properties we1 1 suited f o r MISFET applications. Improvement of the i n t e r f a c e properties of t h i s s t r u c t u r e is obtained by flowing silane on the InP substrate prior to oxide deposition. Interface studies show t h a t s i l a n e reduces the InP native oxides.

1

-

INTRODUCTIOM

Passivation of InP has generated a l o t of e f f o r t s for MIS applications. Since native oxides of InP exhibits e l e c t r i c a l properties w i t h a r e not s u i t a b l e f o r gate d i e l e c t r i c s , there i s a need t o develop appropriate deposited insulators. The techniques proposed t h a t can be sustained by an InP substrate a r e d i r e c t or i n d i r e c t plasma /1,2/, low temperature p y r o l i t i c CVD /3/ and photolytic CVD /4/. However i n a l l cases, there is room f o r improvements i n i n t e r f a c e properties and bulk SiO, structures. When the thermal exposure of an InP substrate i s reduced to a few seconds, the maximum temperature a1 lowed before surface degradation can be considerably increased. In t h i s work, the p c s s i b i l i t y of combining a conventional horizontal CVD reactor w i t h a rapid thermal heatir.9 system using tungsten halogen lamps as a source of radiant heat was explored f o r InP processing. This flash CVD t e c h n i ue named a l s o LRP a f t e r the work of ref. /5/ allows precise control of thermally driven surf& reactions.

In t h i s case the substrate temperature r a t h e r than the flux of reactive gas, i s used as a switch t o turn the CVD reaction on and off. The thermal exposure of the substrate is t h u s minimized. This technique i s a unique opportunity f o r 111-V material t o have access t o high temperature processes such as CvD or LPCvD /6/. Deposition of SiO, was performed on Inp a t 700°C. Following an in-situ cleaning of the InP surface under a SiH, flow.

2

-

EXPERIMENTAL

A flash CVD reactor was designed. I t consists of an horizontal uartz chamber mounted above a row of halogen lamps. The reactor walls are constantly a i r an8 water cooled t o Insure f a s t temperature cycling on the substrate, and avoid undesirable contamination. The possibility to deposit Si02 on InP a t temperatures above 600°C was explored. The reactant gase u t i l i z e d are s i l a n e and oxygen diluted i n flowing nitrogen. The t o t a l pressure of the system is kept constant a t 5 Torr.

A f u l l description of the deposition regimes, and of the kinetics of the reaction obtained on s i l i c o n substrates are described i n ref. /7/. On InP substrates SiOP f i l m are obtained up t o 700°C of substrate tem erature w i t h no degradation of the InP surface. Deposition rates of 100 r l s e c a r e measured'at t h i s temperature w i t h an oxygen t o s i l a n e gas r a t i o of 10. m e t o t a l cycle time f o r a 700 A-thick gate oxide deposited on InP in l e s s than 20 sec, w i t h a temperature r i s e time of 3 sec and a natural cooling time of few seconds. The InP surface

Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988444

(3)

JOURNAL DE PHYSIQUE

which i s usually thermally degraded a t temperatures above 300°C i s preserved here due t o the f a s t temperature cycle and the auto-encapsulation of the substrate i n the f i r s t stage of deposition.

CHARACTERIZATION OF THE SiO, FILMS ON InP

The index of refraction of t h i s oxide was measured t o be 1.46. I t s infrared absorption spec- trum shows t h a t the SiH,+ 0 reaction i s complete w i t h no t r a c e s of Sf-H absorption bands.

The Si-0 s t r e t c h i n g and beniing modes are located respectively a t 1070 and 450 cm-1. These figures are very c10:ie t o the optical c h a r a c t e r i s t i c s of thermally oxidized s i l i c o n films.

InP substrates oriented along the (100) direction w i t h a residual n-type concentration of 7x1015 e/cm3 were carefully prepared f o r e l e c t r i c a l characterization. A 1000W-thick SiO layer was then deposited a t 700°C w i t h the above specified parameters. MIS capacitors wer8 then fabricated on t h i s s t r u c t u r e w i t h the l i f t - o f f of a Ti-Au metal 1 i c film. A r e s i s t i v i t y of 8x1015 a.cm and a breakdown strength of 7 Mv/cm were measured on the oxide layer. Capaci- tance and conductance versus voltage c h a r a c t e r i s t i c s were measured a t 1 MHz. The resulting C ( V ) plot i s displayed i n Fig. la.

As can be seen from t h i s curve accumulation and inversion regimes are easily reached. The residual hysteresis i s 0.8 V which i s a low figure f o r InP based structures. This value does not depend on scanning speed. Capacitance and conductance versus voltage c h a r a c t e r i s t i c s were then taken between 1.0 and 100 Hz. A t these frequencies the d i e l e c t r i c capacitance does not vary and no conductance peaks due t o electron t r a p s a r e observed i n t h i s frequency range.

-10 -5 0 5 10

GATE VOLTAGE ( V ) GATE VOLTAGE (V) ( b )

Fig. 1

.

Capacitance voltage c h a r a c t e r i s t i c a t 1 MHz of a MIS diode fabricated on InP by f l a s h L P ~ V D .

a ) deposition of SiO, on a virgin as polished s u b s t r a t e

b ) deposition of Sf02 a f t e r an in-situ cleaning i n flowing silane.

IV

-

IN-SITU SURFACE CLEANING

One of the major advantages of the f l a s h CVD techniques is t h a t i n - s i t u processing can be e a s i l y accomplished. The substrate i s hot only during deposition or surface reaction and not during purging o r gaz flow s t a b i l i z a t i o n . Different processes can t h u s be made i n - s i t u without cross contamination of one t o the other. Surface preparation p r i o r t o oxide deposition can then be conceived.

The authors have shcmn t h a t an oxidized InP surface exposed t o a s i l a n e flow will r e a c t a t 300°C /8/. Silane changes the bonding of surface InP oxides, restoring covalent bonding through a chemical reaction involving s i l i c o n bonding to InP and taking over the available oxygen t o form Si-0 bonds. This i s i l l u s t r a t e d by the change of AES signal of Indium and Phosphorus of Fig. 2. These spectra indicate t h a t In and P recover t h e i r covalent bonding a f t e r sl 1 ane exposure.

(4)

I I I I

380 390 400 410 90 100 110 120

KINETIC ENERGY lev)

Fig. 2 : Indium and Phosphure Auger spectra f o r d i f f e r e n t treatments o f the InP surface. Thin s o l i d l l n e s represent clean InP surface, dashed l i n e represents oxidized InP surface and t h i c k s o l i d l i n e s represent the restored InP surface s i l a n e exposure. Experiments were performed a t a substrate temperature of 300°C.

The p o t e n t i a l e f f i c i e n c y o f s i l a n e preexposftion o f InP substrates on the improvement o f semiconductor/insulator i n t e r f a c i a l properties has been tested. MIS capacitors have been process with and without s i l a n e i n s i t u cleaning. The cleaning procedure demonstrated i n a UHV environment was transposed t o the f l a s h CVD reactor conditions. It r e s u l t s i n a f l a s h a t 250°C f o r 10 sec i n 0.1 Torr p a r t i a l pressure o f silane. The C ( V ) r e s u l t o f the i n - s i t u clea- n i n g i s shown i n Fig. 1-b. As can be seen, the hysteresis cycle i s lowered by a f a c t o r o f 3 t o a f i n a l value o f 0,25 ev. This improvement o f the hysteresis width can be unambiguovsly assigned t o a reduction o f i n t e r f a c e slow traps.

V

-

CONCLUSIONS

I t has been shown t h a t LPCVD can be c o n t r o l l e d w i t h r a d i a n t heat. This technique opens the access of high temperature processes t o 111-V materials such as InP. Furthermore m u l t i p l e processing steps can be e a s i l y c a r r i e d o u t i n s i t u w i t h i n such a reactor.

REFERENCES

/1/ Meiners, L.G., J. Vac. Sci. Tech., (1982) 665

/2/ Pande K.P. and Nair, V.K.R., J. Appl

.

^~hys.,

⁵⁵

(1984) 3109

/3/ Bennett, B.R., Lorenzo, J.P. and Vaccaro, K., Electron. Lett.,

E,

(1988) 172

/4/ Nissim, Y.I., Regolini, J.L., Bensahel

,

0. and Licoppe, C., Electron. Lett.

2

(1988) 488

/5/ Gibbons, J.F., Gronet C.M. and Williams, K.E., Appl. ~ h y s . L e t t

2

(1985) 721 /6/ Nissim, Y.I. and Bensoussan, M., CNET patent n08614896

/7/ Nissim, Y.I., Bensoussan, M., post G., Bensahel, D. and Regolini, J.L., i n "Photon, Beam and Plasma Enhanced Processing, edited by Golanski, A., Nguyen, V.T. and Krimmel, E.F. (EMRS proc. XV, l e s g d i t i o n s de Physique, Paris, 1987) 213

/8/ Licoppe C., Moison, J.M., Nissim, Y.I., Regolini, J.L., Bensahel, D., submitted t o Appl. ~ h y s . Lett.