HAL Id: hal-01404772
https://hal.inria.fr/hal-01404772
Submitted on 29 Nov 2016
HAL is a multi-disciplinary open access
archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers.
L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.
Accurate Modeling of Fault Impact in Arithmetic Circuits
Pierre Guilloux, Arnaud Tisserand
To cite this version:
Pierre Guilloux, Arnaud Tisserand. Accurate Modeling of Fault Impact in Arithmetic Circuits. DASIP: Conference on Design and Architectures for Signal and Image Processing (Demo Night), Oct 2016, Rennes, France. 2016. �hal-01404772�
Accurate Modeling of Fault Impact in Arithmetic Circuits
Pierre Guilloux and Arnaud Tisserand.
IRISA – CNRS – Univ. Rennes 1
Reliasic
1. Objective: Design of Robust Arithmetic Circuits
Study links between fault detection/tolerant solutions and
I types of operations ±, ×, ×cst, ÷, √, sin, cos, log, . . .
I computation algorithms and representations of numbers
I optimizations at architecture and circuit levels
I mathematical error due to faults and rounding modes
Applications: signal/image processing, embedded computing,
protections for cryptrographic devices, . . .
2. Intensive Logical Fault Simulations: Emulation on FPGA
cells from ASIC library injection controller
x y = x ¯ x 0 1 sel logical fault injector serv er side FPGA side HDL block ASIC tools gate level netlist instrumentation (add injectors) instrumented netlist FPGA tools bitstream FPGA EMULATION 3. Hardware Platform server
FPGA 1 FPGA 2 FPGA N
LAN (switch) GbE links power supply power cables User network 1 server 8 cores 4 GHz 1 power supply 1 GbE switch 4 FPGA Zedbord 7020 1 FPGA PicoZed 7035 1 FPGA Zybo 7010 Total cost 3800 eHT
4. Emulation Engine(s) in FPGA
reference block BUE PI distribution module on-line analysis module interface injection CTRL main CTRL x y ˜ y ARM core ARM core AXI bus emulation engine 1 emulation engine 2 PS PL
reference operator computes y = f (x )
faulted operator computes y = ˜f(x )e
mathematical error analysis ε = |y − ˜y |
5. Tools Flow
FPGA 1 FPGA 2 FPGA N
cell library ASIC tools FPGA tools bitstream definition step block emulation directives serv er side FPGA side Platform preparation
step emulationstep
results analysis
Possible locations for logical fault injection:
I manual on selected internal nets (for debug)
I random on internal nets
I random over circuit area (based on cells area)
6. Example: Multiplier with Residue Code Detection
16×16-bit integer multiplier, moduli m ∈ {3, 7, 15}, with
(a × b) mod m = (a mod m) × (b mod m) mod m
step duration area delay
Impl. ASIC orig. mult. 25 s 1164 gates –
Impl. FPGA orig. mult. 43 s 444 LUT 9.4 ns
Impl. FPGA instrum. mult. 48 s 453 LUT 10.1 ns
Impl. FPGA emul. engine 389 s 1714 LUT + 1 BRAM 11.0 ns
boot petalinux Zedboard 15 s – –
emulation 1 fault & 1 EE 94.5 s – –
Comparaison to a CABA simulation in software (Vivado 2014.4) :
×6880 speedup for 1 emulation engine
Error distribution for exhaustive tests (232 inputs) and various
sin-gle faults (1 color = 1 fault) :
0 20 40 60 80 100 0 5 10 15 20 25 30 35 40 frequency [%]
error [bin index in 0..255]
Residue code implementation results:
modulo area delay mesured avg. detection rate
m [LUT] [ns] [%]
3 525 10.4 66.7
7 526 10.1 85.6
15 553 13.0 93.3
7. Future Works
100 EEs @ 100 MHz / second / hour / day
nb. faults or PIs 100 · 106 × 100 ≈ 233 ≈ 245 ≈ 249
References:
Arithmetic operators library from R. Zimmermann (http://www.iis.ee.ethz.ch/ zimmi/arith_lib)
P. Guilloux & A. Tisserand, Compas 2016, French Conf. on Parallelism, Architecture and System
