HAL Id: hal-02893131
https://hal.telecom-paris.fr/hal-02893131
Submitted on 16 Jul 2020
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Interactive System Level Debugging of Systems-on-Chip
Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet
To cite this version:
Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet. Interactive System Level Debugging of Systems-on-Chip. S4D, Sep 2010, Southampton, United Kingdom. �hal-02893131�
Mapping
(2) Architecture modelling
Simulation
DIPLODOCUS: A 3-step Methodology Environment based on UML
Hardware architecture is modeled using generic hardware components (CPUs, buses, hardware accelerators)
(1) Application Modelling
System is modeled in terms of communicating tasks (UML class diagram)
Behavior modeling is focused on control part of the application (UML activity diagrams)
Interactive System Level Debugging
of Systems-on-Chip
Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet
{daniel.knorreck, ludovic.apvrille, renaud.pacalet}@telecom-paristech.fr
System-on Chip Laboratory (LabSoC), Institut Telecom, Telecom ParisTech, LTCI CNRS 2229 Route des Crêtes, B.P. 193 F-06904 Sophia Antipolis, France
(3) Application mapped onto an architecture
Refinement Simulation
Formal static analysis
Fast transaction-based simulation
For further information: http://www.comelec.enst.fr/recherche/labsoc.en
An open-source
toolkit – called TTool –
fully supports this methodology.
Computation and communication events are represented by symbolic instructions and span potentially hundreds of clock cycles Simulation granularity automatically adapts to the granularity of the application
Instructions are executed as a whole if possible, they may be broken down into several transactions due to inter-task
synchronization
Fully implemented in C++, possibility to generate traces in VCD format Possibility to save and restore simulation states
Interaction of Frontend and Simulator
Simulator Design
Execution HW
Discrete Event Simulator
Task model
For a car communication application, we achieved an order of magnitude of simulation speed of
Billions of cycles/sec.
A more fine grained model of an MPEG decoder led to a rate ofMillions cycles/sec.
Abstract Channels Communication HW Transaction: Start TimeVirtual Length [Ex. units] Length [Time units]
Model Semantics
HW Semantics
Static formal analysis Formal semantics
Fast Simulation
Used by industrial partners Variable Application Coverage
