HAL Id: tel-01620216
https://tel.archives-ouvertes.fr/tel-01620216
Submitted on 20 Oct 2017HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or
L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires
transistors
Wenlin Kuai
To cite this version:
Wenlin Kuai. Feasibility of solution processed organic field-effect transistors. Micro and nanotechnolo-gies/Microelectronics. Université Rennes 1, 2017. English. �NNT : 2017REN1S013�. �tel-01620216�
ANNÉE 2017
THÈSE / UNIVERSITÉ DE RENNES 1
sous le sceau de l’Université Bretagne Loire
pour le grade de
DOCTEUR DE L’UNIVERSITÉ DE RENNES
1
Mention : ElectroniqueEcole doctorale MATISSE
présentée par
Wenlin KUAI
préparée à l'unité de recherche IETR- UMR CNRS 6164
Institut d'Electronique et de Télécommunication de Rennes
UFR Informatique – Electronique
Intitulé de la thèse :
Faisabilité de
transistors organiques
à effet de champ
fabriqués entièrement
en solution.
Thèse soutenue à Rennes le 23 janvier 2017
devant le jury composé de :
Claude PELLET
Professeur, Université de Bordeaux / rapporteur
Yvan BONNASSIEUX
Professeur, Ecole Polytechnique Palaiseau / rapporteur
Byuong Seong BAE
Professeur, Hoseo University, Corée / examinateur
Mireille RICHARD-PLOUET
HdR, CR-CNRS, IMN Nantes / examinatrice
Florence GENESTE
DR-CNRS Université Rennes 1 / examinatrice
Maxime HARNOIS
IR-CNRS, Université Rennes 1 / co-directeur de thèse
Tayeb MOHAMMED-BRAHIM
Faisabilité de transistors organiques à effet de champ fabriqués
entièrement en solution
Feasibility of fully solution deposited OFETs
Présentée par Wenlin KUAI
Résumé
Ces dernières décennies, des efforts de recherches considérables ont étés mis en œuvre afin de répondre aux nouveaux défis sociétaux (i.e., énergie durable, utilisation efficace de matières premières, santé, mobilité…) ainsi qu’aux nouveaux modes de consommation (i.e., objets connectés, écrans grande surface et/ou souples…). Ainsi, devraient voir le jour dans un future proche : i) des écrans souples transparents et couvrant de grandes surfaces, ii) des panneaux photovoltaïques souples iii) des capteurs connectés souples enregistrant des constantes physiologiques au plus près des patients… Les acteurs de l’électronique, multinationales et laboratoires de recherche, s’efforcent de proposer de nouvelles technologies permettant de satisfaire ces nouveaux besoins. L’une d’elle, développée depuis une décennie et communément appelée « électronique imprimée », est un sérieux candidat pouvant répondre aux problématiques actuelles citées précédemment.
L’électronique imprimée, met en œuvre des matériaux en solution (encres : polymériques, semiconductrices, à base de nano-objets…) en utilisant des équipements déjà éprouvés dans l’art graphique. Cependant, les savoir-faire acquis dans le domaine de l’impression doivent être transférés vers « le monde de l’électronique » où la réalisation de motifs miniatures et la qualité de transport électronique sont des paramètres importants. Cette
problématique, constituant un enjeu majeur, a donné naissance à cette étude. En effet, la
méthodologie de conception des dispositifs électroniques imprimés est différente de celle utilisée en « électronique conventionnelle ». Concrètement, un dispositif électronique
imprimé est réalisé de façon additive (chaque couche le constituant est déposée l’une après l’autre et ne nécessite aucune étape de gravure) contrairement à un dispositif réalisé par photolithographie où les couches sont déposées sur une grande surface puis gravées pour définir des motifs (procédé communément utilisé en microélectronique). De plus, l’électronique imprimée peut adresser d’autres challenges tels que : la réalisation à basse température d’électronique sur des substrats non-conventionnels et de grande surface (plastique, papier, biodégradable…). Des premiers transistors entièrement imprimés ont étés réalisés en laboratoire, mais, à ce jour, aucun produit n’a été commercialisé en utilisant cette technologie. En effet, de nombreux verrous restent à lever tels que : la fiabilité, la reproductibilité de fabrication et de performance des dispositifs.
Le laboratoire a acquis par le passé une expérience solide sur la réalisation par lithographie de transistors sur substrat flexible et plus récemment de transistors organiques réalisés par évaporation. La technologie organique est un candidat de choix pour réaliser des transistors entièrement en solution. En effet, tous les matériaux constituant un transistor peuvent être « mis en solution ». Des encres à base de nanoparticules ou de polymères conducteurs, d’isolants polymériques et de semiconducteurs organiques solubles peuvent être utilisées respectivement comme électrodes de contact, isolant de grille et couche active. Par conséquent, Cette étude a pour but d’étudier la faisabilité de fabrication de transistors
organiques entièrement en solution et à terme entièrement imprimés. La démarche
scientifique suivie lors de cette étude consistera en :
L’étude et l’optimisation des paramètres expérimentaux permettant de fabriquer des transistors organiques réalisés par photolithographie dont le semiconducteur solubilisé a été déposé en solution (par « drop casting »).
L’étude de faisabilité de transistors organiques entièrement imprimés
L’étude d’une nouvelle fonctionnalisation chimique de surface permettant d’améliorer les caractéristiques électriques des transistors.
Dans la première partie de ce travail, des structures « bottom gate-bottom contact » ont été réalisées par photolithographie. Ces structures dont la technologie est maitrisée au laboratoire, ne sont pas réalisées entièrement en solution (cf figure 1). Cependant, elles
couche active de semiconducteur organique déposée en solution (drop-casting).
Figure 1 : Illustration d’un transistor organique (structure « bottom gate-bottom contact »). Dans le cadre de notre étude les matériaux et les techniques de dépôt utilisés sont les suivants : contact de grille en aluminium déposé par évaporation thermique, contact drain et
source en or déposé par évaporation thermique ; isolant de grille (Su8) déposé par « spin-coating » (en solution) ; semiconducteur déposé par « drop-casting » (en solution)
Le C60 de conduction de type n et le Tips-pentacene de conduction de type p, deux
semiconducteurs organiques, ont été choisis comme couche active de transistors de type n et de type p aboutissant à une électronique CMOS entièrement en solution. Pour chaque type de semiconducteur, l’effet des paramètres expérimentaux (type de solvant, température de séchage et de recuit du semi-conducteur) sur la réponse électrique des transistors organiques a été étudié. Aussi, une analyse morphologique des semiconducteurs organiques a démontré que la nature des solvants à un impact drastique sur la morphologie des cristaux des semiconducteurs mais aussi sur la valeur du courant de de fuite de grille IGS.
Semiconducteur Solvant μ(cm2/Vs) VTH (V) SS (V/dec) Ion/Ioff
C60 Dichlorobenzene 0.018 31.5 12.64 105
Tips-pentacene Chlorobenzene 0.094 -2.1 2.7 103
Tableau 1: Principaux paramètres, mobilité µ, tension de seuil VTH, pente sous le seuil SS et rapport courant direct sur courant inverse ION/IOFF, extraits des caractéristiques électriques de transistors organiques dont le semiconducteur C60 dissous dans du dichlorobenzene ou Tips-pentacene dissous dans du chlorobenzene, a été déposé par « drop casting » et dont les
paramètre expérimentaux ont été optimisés.
D’autres, part une analyse du courant de grille IGS a montré qu’il était dépendant du
solvant solubilisant le semiconducteur (cf figure 2)
Figure 2 : Caractéristique de transfert courant drain-source IDS en fonction de la tension grille-source VGS et courant de fuite de grille IGS des transistors organique en fonctions du
type de solvant utilisé pour diluer le semiconducteur (Tips-pentacene).
Ce résultat a été confirmé par des mesures de capacités MIM (métal/isolant/métal) dont l’isolant a subi un traitement à base de solvant. Nous avons émis l’hypothèse que le solvant pouvait « endommager chimiquement » l’isolant polymérique. Cette première partie a permis de déterminer les paramètres expérimentaux optimaux concernant la dilution des semiconducteurs et de soulever le problème du fort courant de grille IGS. Ce dernier étant
néfaste pour un fonctionnement optimal des transistors, une solution originale pour le réduire a été proposée et sera décrite par la suite.
La seconde partie de ce travail traite de l’impression jet d’encre. Cette technologie, nouvelle pour le laboratoire, a nécessité une étude portant sur le choix et la mise en œuvre des matériaux. Chaque matériau constituant le transistor organique a été caractérisé vis à vis de l’éjection, de l’imprimabilité, de sa morphologie et de ces propriétés électriques.
En ce qui concerne les électrodes de grille et de drain/source, une encre commerciale à base de nanoparticules d’argent a démontré la possibilité de réaliser : i) des pistes de résistivité comparable à la littérature (2.5*10-5 ohm.cm), ii) une largeur de piste minimum de
60µm, iii) une distance reproductible entre deux pistes de 60µm, iv) une température de recuit de 120°C compatible avec la température maximale acceptable d’un substrat plastique, type PEN.
Concernant l’isolant de grille, l’étude a permis de démontrer la versatilité d’une encre polymérique (Su-8) d’un point de vue de l’éjection (sur une large gamme de concentration en polymère (1 à 15cp) et de l’imprimabilité (après traitement chimique de surface par UV/ozone). De plus, plusieurs scripts d’impression (en activant une ou plusieurs buses d’impression simultanément) ont montré la possibilité de contrôlé l’épaisseur de la couche isolante. Par conséquent, des structures « bottom gate-bottom contact » non-entièrement imprimées ont été réalisées (figure 3) et testées avec un semiconducteur évaporé afin de montrer la faisabilité de la structure (grille/isolant/drain-source) dans un premier temps. Un récapitulatif des paramètres (μ, VTH, SS, Ion/Ioff) extraits des caractéristiques électriques d’un
Figure 3: Images optiques des structures « bottom gate-bottom contact » non entièrement réalisées par impression (électrodes et isolant imprimés, semiconducteur évaporé) : (a)
isolant réalisé en activant une buse d’impression; (b) Zoom sur les bords de l’isolant correspondant au transistor décris en (a); (c) Zoom sur le canal du transistor décris en (a); (d)
isolant réalisé en activant plusieurs buses d’impression; (e) Zoom sur les bords de l’isolant correspondant au transistor décris en (d); (f) Zoom sur le canal du transistor décrit en (d).
μ(cm2/Vs) VTH (V) SS (V/dec) Ion/Ioff
0.0059 21.76 4.72 104
Tableau 2: Exemple de caractéristique électrique d’OFET imprimé en activant plusieurs buses d’impression et un isolant d’épaisseur 1µm.
La structure étant validée, des tests de transistors entièrement en solution ont été réalisés mais un phénomène de démouillage du semiconducteur (déposé par drop casting) sur les électrodes drain/source a été observé. Par conséquent, la couche active de semiconducteur n’était pas continue entre les électrodes (cf figure 4a). Une méthode originale a été proposée pour résoudre ce problème. L’idée consiste à ajouter un polymère en faible quantité dans la solution semiconductrice afin de piéger la ligne de contact du semiconducteur liquide (cf figure 4b).
Figure 4: Images optiques du semiconducteur deposé par “drop casting” sur des electrodes imprimées: a) couche non continue de semiconducteur après sechage d’une goutte de tips-pentacene dilué dans son solvant; b) couche continue de semiconducteur après sechage d’une
goutte de tips-pentacene dilué dans : i) son solvant et ii) une faible quantité de polymère (5% en volume de Su8).
Des transistors entièrement imprimés ont été réalisés mais leur comportement électrique, bien que prometteur, n’a pas montré un comportement électrique compatible avec la réalisation de circuit électronique de type inverseur, par exemple. Par conséquent, une étude plus approfondie de la dilution de polymères est indispensable et sera effectué dans des travaux ultérieurs.
La troisième partie de ce travail a consisté en l’étude et la mise au point d’une nouvelle fonctionnalisation de surface de l’isolant polymérique dans le but de réduire le courant de fuite IGS. Le greffage de l’1-aminoanthraquinone sur l’isolant a été étudié d’un
point de vue : rugosité, énergie de surface et polarité. L’impact de la fonctionnalisation de surface sur les transistors a été estimé en réalisant des caractérisations électriques (caractéristique de transfert, de sortie et de stabilité électrique). Comme le montre la figure 5, la mobilité des transistors est considérablement augmentée (1 décade) lorsque les transistors sont fonctionnalisés. De plus, et ce qui est particulièrement important, le courant de fuite de grille a été largement réduit (Figure 6).
Figure 5: (a) Caractéristiques de transfert avec et sans fonctionalisation (b) dispertion de la mobilité avec et sans modification de surface
Figure 6: Courant de fuite de grille en fonction de la tension grille pour un transistor dont l’isolant de grille SU8 n’a pas été (courbe en noir) ou a été (courbe en rouge) fonctionnalisé
avant le dépôt de la couche active semiconductrice.
En conclusion cette thèse constitue une très large revue de la problématique et des difficultés à surmonter dans la recherche d’un procédé fiable et reproductible de fabrication de transistors entièrement en matériaux organiques déposés par impression à jet d’encre. Des solutions ont été trouvées et de nouvelles idées proposées. Cependant beaucoup de travaux sont encore nécessaires.
Table of contents
Introduction ... 1
Chapter 1: OTFTs: General Points ... 5
I Introduction ... 6
II Development of Organic Thin-film Transistors (OTFTs) ... 7
III Principle and deposition methods of organic semiconductor ... 10
III.1 Principle of organic semiconductor ... 10
III.2 Deposition methods of organic semiconductor ... 11
IV Basics and structures of OTFTs ... 19
IV.1 Basics of OTFTs ... 19
IV.2 Structures of OTFTs ... 21
V Characteristics and parameters extraction of OTFTs ... 23
V.1 Characteristics of OTFTs ... 23
V.2 Parameters extraction of OTFTs ... 28
VI Thesis organization ... 29
Reference ... 30
Chapter 2: N-type and p-type drop casted organic semiconductors on OTFT: processing and characterization ... 39
I Introduction ... 40
II. Issues of solution processing ... 40
II.1 Effect of solvents ... 40
II.2 Effect of drying and annealing temperature ... 45
II.3 Effect of surface functionalization (SAMs)... 47
III OTFTs processing ... 48
IV N-type solution processed OTFTs ... 50
IV.1 Effect of solvent of C60 OTFTs ... 50
V P-type solution processed OTFTs ... 54
V.1 Effect of Tips-pentacene solvent ... 54
V.2 Effect of drying and annealing temperature of Tips-pentacene OTFTs ... 63
V.3 Effect of a functionalization of drain and source contacts on Tips-pentacene OTFTs 65 V.4 Structure factors: Effect of channel length of Tips-pentacene OTFTs ... 67
Conclusion ... 69
Reference ... 70
Chapter 3: Inkjet-printing ... 73
Part I: Technique and methodology ... 75
I.1 Printed electronics ... 76
I.1.1 Applications ... 76
I.1.2 Printing techniques... 78
I.2 Inkjet printing ... 81
I.2.1 DoD Technology ... 83
I.2.2 Inkjet printing key steps: Jetting, Spreading, Wetting and Drying. ... 84
I.2.3 Inkjet printing system and characterization methods ... 95
Part II: Inkjet printed OTFTs... 103
II.1 Printability of OTFT functional materials ... 104
II.1.1 Conductive ink ... 104
II.1.2 Insulator Ink ... 120
II.1.3 Semiconductor ink ... 129
II.2 Printed OTFT ... 130
II.2.1 Feasibility of first printing steps (gate contact, gate insulator, source and drain contacts): OTFTs with evaporated semiconductor... 130
II.2.2 Feasibility of solution deposited OTFTs: Printed gate contact, gate insulator, source and drain contacts, Drop-casted Tips-pentacene ... 135
Conclusion ... 145
Reference ... 147
Chapter 4: Can surface modification improve the characteristics of solution-processed OTFTs? Example of functionalization with 1-aminoanthraquinone ... 153
I. Introduction of surface modification of OTFTs ... 154
I.1 Main factors at the semiconductor-insulator interface ... 154
II. Experimental process of Su8 surface modification with 1-aminoanthraquinone ... 158
II.1 Materials ... 158
II.2 OTFT fabrication and 1-aminoanthraquinone grafting process ... 159
III. Characteristics of Su8 surface after grafting ... 160
III. 1 Surface roughness of dielectrics ... 160
III. 2 Surface energy and surface polarity of the dielectrics ... 163
III.3 Dielectric constant ... 165
IV. Electrical properties in OTFTs modified with 1-aminoanthraquinone ... 166
IV.1 Electrical parameters of OTFTs ... 166
IV.2 Stability of OTFTs ... 167
Conclusion ... 174
Reference ... 175
Introduction
Introduction
lexible electronics becomes now a major research domain due to a fast growing market. The market of wearable technology was $24 billion in 2015 and it is expected to grow over $70 billion in 2025 [1]. Only the e-textiles market will grow by 68% rate reaching $3 billion in 2026 [2]. These data cover in fact a lot of fields, technologies and materials. Robotics [3],
health monitoring [4], epidermal electronics [5], e-textile [6], displays [7] are the main targeted fields.
Flexible or even stretchable devices need ultra-flexible materials. The first parameter indicating the flexibility of a material is its Young modulus. Young modulus is in the range of 0.1-10 GPa [8] for organic materials. It is higher than 100 GPa for inorganic oxide based
semiconductors (130 GPa for the most used oxide IGZO [9]) and around 160 GPa for silicon.
With their very low Young modulus, organic materials are considered fitting perfectly the need of flexibility.
This is why numerous studies on organic materials based electronic devices were made in the last 2 decades. Particularly the first element of any electronics that is the transistor was, since 1986, and continue to be the subject of major research in the world.
Field Effect Transistor, particularly in its thin film structure, is a stack of different thin films, mainly the semiconducting active layer, the gate insulator and the gate contact. Major works in the world on these Organic Thin-Film Transistors (OTFTs) focus only on the need to have organic semiconducting active layer; the other insulating and conducting films are made of inorganic materials. In the main idea to get highly flexible device, it is more important to focus on fully organic TFT where all the layers are made on organic materials in the purpose to benefit from the low Young modulus of these materials.
The present PhD thesis focuses on this main purpose, trying to determine the main parameters influencing the performance of fully organic TFT.
In this trying, the work considers the need to use the lowest cost but highest reproducibility techniques. Indeed, the main interest of flexible electronics is its use in lowest cost and large public products.
Deposition of thin films by solution techniques at ambient temperature, avoiding vacuum techniques, will lead to lowest cost devices.
Solution techniques are numerous. We can take as examples spin coating, drop casting, printing…From all these techniques, inkjet printing becomes more and more attractive thanks to the low used volume inducing low cost, the reproducibility that is the main issue of such techniques and the use of software design avoiding the need of hard mask. Most of studies on solution processed OTFTs are devoted on this technique.
The present work focuses on solution processed OTFTs fabricated by using drop casting and inkjet printing to achieve high electrical performance, electrical stability and reproducibility. Drop casting was used only as a first step in determining the main parameters influencing the process of solution deposited OTFTs.
The work benefited from the great experience of IETR in thin film electronics, particularly in silicon based devices. This experience was extended some years ago on organic TFTs using evaporated organic semiconducting active layer, organic insulator and inorganic metallic contacts [10]. The present work continues this trend towards low cost and low
temperature processed electronics.
The thesis is organized in 4 chapters.
In the first chapter, the development of OTFTs will be introduced. The principle and deposition methods including vacuum deposition and solution processing of organic semiconductor will be described. Afterwards, a brief description of solution-processed OTFTs will be given. The basics, the structure, the characteristics and parameters extraction of OTFTs are detailed.
In the second chapter, drop casted OTFTs will be introduced. N-type OTFTs based on C60 and p-type OTFTs based on Tips-pentacene will be detailed. Issues of solution processing,
including solvent effect, drying and annealing temperature effect, and surface functionalization effect will be firstly presented. The processing of OTFTs will be introduced. Depending on the issues of solution processing, solvent effect, drying and annealing temperature effect, and surface functionalization effect will be presented in detail.
In the third chapter, inkjet printed OTFTs will be presented. This chapter consists of two major parts.
Part I is dealing about technique and methodology of inkjet printing. Printed electronics, including applications and printing techniques will be first detailed. Inkjet printing technology as well as printing key steps, printing system and characterization methods will be detailed in the second section.
Introduction
Part II is dealing about inkjet print OTFTs. The printability of OTFT functional materials, including conductive ink, insulator ink, and semiconductor ink will be presented. The OTFT fabrication, as well as printing methodology for stacked layers structure, and electrical characterization will be presented in the second section.
In the fourth chapter, a method to improve the characteristics of solution processed OTFTsusing surface modification of the Su8 gate insulator by 1-aminoanthraquinone before depositing the semiconducting active layer, will be introduced. Principle of surface modification at the interface between the active layer and the gate insulator in OTFTs process will be firstly introduced. Indeed, charge carrier transport between source and drain in OTFTs is restricted by the first several semiconductor monolayers next to semiconductor-insulator interface. Thus, the surface of insulator is critical for the electrical performance of the transistors. Main factors at the semiconductor-insulator interface, including surface roughness, surface energy, surface polarity and dielectric constant will be detailed. Then first trying to change the interface between the semiconductor and the insulator in present OTFTs is introduced by functionalizing the surface of Su8 gate insulator by 1-aminoanthraquinone.
Finally, the thesis is concluded by remembering the main results and presenting the way to continue this work leading to functional solution processed organic electronics.
Reference
[1] P. Harrop, J. Hayward, R. Das, G. Holland, “Wearable Technology 2015-2025: Technologies, Markets, Forecasts” IDTechEx report, 2015.
[2] J. Hayward “E-textiles 2016-2026: Technologies, markets and Players” ” IDTechEx report, 2015.
[3] T. Someya, Y. Kato, T. Sekitani, S. Iba, Y. Noguchi, Y. Murase, H. Kawaguchi, T. Sakurai, “Conformable, flexible, large-area networks of pressure and thermal sensors with organic transistor active matrixes” Proc. Nat. Acad. Sci. vol.102, 2005, pp. 12321-12325.
[4] S. Jung, T. Ji, V.K. Varadan, Point of care temperature and respiration monitoring sensors for smart fabric applications, Smart Mater. Struct. vol. 15, 2006, pp.1872-1876.
[5] D. H. Kim et al, “Epidermal electronics”, Science vol.333, 2011, pp. 838.
[6] R.B. Katragadda, Y. Xu, “A novel intelligent textile technology based on silicon flexible skins”, Sens. Actuators A vol.143, 2007, pp. 169-174.
[7] G. Chansin, K. Ghaffarzadeh, H Zervos, “OLED Display Forecasts 2015-2025: The Rise of Plastic and Flexible Displays” IDTechEx report, 2015.
[8] B. H. Stuart, Polymer Analysis, Wiley 2002.
[9] T. Yoshikawa, T Yagi, N. Oka, J. Jia, Y. Yamashita, K. Hattori, Y. Seino, N. Taketoshi, T. Baba, Y. Shigesato, Appl. Phys. Express vol 6, 2013, pp.021101-1/3.
[10] S. Beniche, “OTFTs de type N à base de semiconducteurs π-conjugués : Fabrication, performance et stabilité”, thèse de doctorat, Université de Rennes 1, 2015.
Chapter 1: OTFTs: General Points
I Introduction
As explained in the introduction of this thesis, the present work deals with the development of new organic electronics based on solution fabricated electronic circuits. It focuses on the first element of any electronics that is the transistor and particularly on the field effect transistor. Field effect transistor is a stack of different thin films when dealing with large-area electronics fabricated on any substrate and using different semiconductor materials as silicon, metal oxides or organics. In this case, the transistor is named Thin Film Transistor (TFT).
Thin Film Transistor is based on the modulation of the current flowing in a semiconductor material between 2 electrodes, named source and drain, by a bias applied on a third electrode, the gate, that is electrically insulated from the way between drain and source electrodes by an insulator (or dielectric) material. A structure of TFT in bottom gate, bottom contacts configuration is given in the scheme of Figure 1-1. Present work will focus on this configuration. However, other configurations are possible and will be presented in the next. The choice of the configuration of Figure 1-1 will be also explained.
Figure 1-1: Structure of Thin Film Transistor presented here in the bottom gate, bottom contacts configuration.
In the ideal, under some gate voltage no current flows between source and drain contacts. In this case, the transistor is in its off-regime. Under other gate voltage the maximum current has to flow between source and drain contacts and the transistor is in its on-regime. In practical, low current Ioff flows in off-regime and lower is this current best
Chapter 1: OTFTs: General Points
In on-regime the performance is quantified by the maximum current Ion flowing
between source and drain.
Hence, in high performance TFT, Ioff has to be as low as possible and Ion as high as
possible. The ratio Ion/Ioff is a good factor to evaluate the quality of a TFT.
The value of the on-current Ion depends on:
The external parameters: gate voltage, voltage between source and drain contacts.
The physical parameters: charge transport parameters of the semiconducting material between source and drain, the electrical quality of the interface between the insulator and the semiconductor as the different films are very thin.
The geometrical dimensions: the distance between source and drain contacts (named L for length) and the length of the drain and source electrodes (named W for width of the transistor).
Higher on-current is given by the best charge transport parameters of the semiconducting material (that means the highest charge carrier mobility) for the same geometrical dimensions and the same applied voltages.
After this brief introduction on the principle of a transistor, we have now to introduce the organic based TFT or OTFT
II Development of Organic Thin-film Transistors (OTFTs)
Compared to inorganic-semiconductor based transistors [1-3], the study of organic
semiconductor based transistors [4] started more recently. Before the use of organic
semiconductor as active layer for transistor, researchers have focused on material properties. In 1832, Jacob Berzelius firstly used the polymer as organic material [5]. It is
well-known that polymers have an insulator behavior. Consequently, experiments performed on polymer’s conductivity improvement have been carried out since the end of the 18th. In 1862, Henry Letheby succeeded to fabricate a partly conductive “blue substance” [6]. Moreover, in
1906, Pochettino reported the photovoltaic effect in anthracene [7]. Such organic molecule was widely used in the following decades for the interpretation of physical properties. Until the second half of the 19th, Akamatu obtained a conductive organic material: the perylene [8]. It has a relatively good electrical conductivity (10-3 S/cm). Preliminary studies dealing with
work focused on the fabrication of new polymers with longer organic molecules and in order to improve electrical performance.
In the same period, another route of research on organic semiconductor materials was the investigation of π-conjugated materials. Hideki Shirakawa obtained a conductive transpolyacetylene, with conductivity of 30 S/cm [10].
After 30 years of study on polymers [11, 12] and small molecules [13, 14], Richard Friend
and Francis Garnier have fabricated organic transistors, in 1988 [15] and 1990 [16], respectively.
They have contributed greatly on the development of Organic Field-Effect Transistors (OTFTs).
One of the most important electrical parameters of organic transistors is carrier mobility [17]. The development of the field effect mobility of both p-type and n-type transistors
based on small molecule and polymer is summarized in Figure 1-2 [17]. It can be observed that
the motility has been improved continually for both p-type and n-type and both vacuum-processed and solution-vacuum-processed during the past 30 years.
Figure1-2: Development of the carrier field-effect mobility of p-channel and n-channel transistors based on small molecule and polymeric semiconductors.
Vacuum-processed technique and solution-processed technique are two main methods for depositing organic semiconductors [18]. Table 1-1 lists the highest field-effect mobility (μ)
Chapter 1: OTFTs: General Points
Year Mobility
(cm2/Vs) Material (deposition method) (v) = Vacuum deposition
(s) = From solution Ion/Ioff W/L Ref 1983 Minimal, NR Polyacetylene (s) NR 200 [19] 1986 10-5 Polythiophene (s) 103 NR [20] 1988 10 -4 Polyacetylene (s) 105 750 [21] 10-3 Phthalocyanine (v) NR 3 [22] 10-4 Poly (3-hexylthiophene) (s) NR NR [23]
1989 1010-3 -3 Poly (3-alkylthiophene) (s) A–v-hexathiophene (v) NR NR NR NR [24] [25]
1992 2×100.027 -3 A–v-hexathiophene (v) Pentacene (v) NR NR 100 NR [26] [43] 1993 0.05 A–v-dihexyl-hexathiophene (v) NR 100-200 [30] 0.22 Polythienylenevinylene (s) NR 1000 [28] 1994 0.06 0.03 A–v-dihexyl-hexathiophene (v) A–v-hexathiophene (v) >10NR 6 50 21 [29] [30] 1995 0.038 0.3 Pentacene (v) C60 (v) 140 NR 1000 25 [31] [32] 0.02 Phthalocyanine (v) 2×105 NR [33] 1996 0.045 Poly (3-hexylthiophene) (s) 340 20.8 [34] 1997 0.13 A–v-dihexyl-hexathiophene (v) >104 7.3 [35] 0.62 Pentacene (v) 108 11 [36] 1.5 Pentacene (v) 108 2.5 [37] 0.05 Bis(dithienothiophene) (v) 108 500 [38] 1998 0.1 Poly (3-hexylthiophene) (s) >10 6 20 [39] 0.23 A–v-dihexyl-quaterthiophene (v) NR 1.5 [40] 0.15 Dihexyl-anthradithiophene NR 1.5 [41] 2000 0.1 N-decapentafluoroheptyl-methylnaphthalene- 1,4,5,8-tetracarboxylic diimide (v) 10 5 1.5 [42] 0.1 A–v-dihexyl-quaterthiophene (s) NR NR [42] 0.89 Pentacene precursor (s) 4.4×105 313 [43] 2002 0.66 BP2T (v) 2×104 80-200 [44] 3 Pentacene (v) 105 1.3 [45]
2003 5.5 TES ADT Pentacene (s) 106 NR [46]
2004 1 Pentacene (v) 108 NR [47]
7 Pentacene (v) 106 NR [48]
2005 0.7 Rubrene (s) 106 NR [49]
1.2 Tips-pentacene (s) 108 5.5 [50]
2006 0.72 Thieno-thiophene (s) 106 NR [51]
2007 3 Fluorinated F-TES ADT (s) 107 NR [52]
2009 3.8 Pentacene (v) 102 10 [53]
2011 8.85 Pentacene (v) 103 10 [54]
2012 10.5 5 DPP-DTT-based polymer (s) PF-TAA (s) 10106 6 28 22 [55] [56]
2013 3.5 6.8 12 NDI-DTYMI (s) Tips-pentacene:ο-Meo-DMBI (s) P-29-DPPDTSE (s) 108 106 106 28-280 20 NR [57] [58] [59]
Year Mobility
(cm2/Vs) Material (deposition method) (v) = Vacuum deposition
(s) = From solution Ion/Ioff W/L Ref 2014 1.7 1.1 6.3 14.4 43 FBDPPV-1 (s) DNTT (s) DBPy (s) PTIIG-NP (s) C8-BTBT (s) 106 107 103 105 103 20 5 33 50 10 [60] [61] [62] [63] [64] 2015 6.7 diF-TES-ADT (s) 105 12.5 [65] 2016 11.1 6.8 Tips-TAP (v) Tips-TAP (s) 10107 7 10 10 [66] [66]
Values for Ion/Ioff correspond to different gate voltage ranges and thus are not readily comparable to one another.
NR = Not reported
Table 1-1: Highest field-effect mobility (μ) values measured from OTFTs as reported in the literature annually from 1983 to 2016.
It can be observed that the mobility increased from 10-5 to 43 cm2/Vs. Moreover, lots
of organic materials were used as active layer in transistors. Solution-processed OTFTs have attracted interests of scientific research and industry, because of its low cost, and low temperature fabrication process. Furthermore, solution-processed organic semiconductor is a serious candidate in order to achieve equivalent field effect mobility than vacuum-processed technique.
III Principle and deposition methods of organic
semiconductor
In this section, the working principle of organic semiconductor will be introduced firstly. The deposition methods of organic semiconductor including vacuum deposition and solution process will be presented. Moreover, solution-processed deposition method will be presented in detail.
III.1 Principle of organic semiconductor
The energy scheme in Figure 1-3 (a) shows: the respective positions of the Fermi level of gold, the lowest unoccupied molecular orbital (LUMO) and the highest occupied molecular orbital (HOMO) of pentacene. As can be seen in Figure 1-3 (a), the LUMO level of pentacene is quite far away from the Fermi level of gold than the HOMO level. Consequently,
Chapter 1: OTFTs: General Points
although negative charges will be induced at the source, barrier height is too high to inject electron. In contrast, when a negative voltage is applied to gate, holes are easily injected from HOMO to gold. Due to this fact, pentacene is said to be p-type.
On the contrary, an organic semiconductor is said to be n-type when electron injection is easier than hole injection, which occurs when the LUMO level is closer to the Fermi level than the HOMO level.
Organic semiconductors are conjugated π-electron systems with sp2 hybridized carbon-carbon bonds. Figure 1-3 (b) shows the classic example of a benzene ring. π-electron cloud is formed between π-orbitals, allowing for the delocalization of electrons through bond resonance. The orbitals are out-of-plane with the atoms, meaning that the conjugated π-electron cloud can interact with π-π-electron clouds on neighboring molecules. Due to the interaction, periodicity of molecules can result in a split of the molecular orbitals into energy bands (i.e. HOMO energy band and LUMO energy band).
Figure 1-3: (a) Energy diagrams of Au/pentacene interface, (b) Schematic illustration of the orbital hybridization in a benzene ring [67].
III.2 Deposition methods of organic semiconductor
There are many deposition methods in OTFT fabrication process. Each method has its own specific feature and application. Here, two different deposition methods will be presented: vacuum deposition and solution-processed deposition.
III.2.1 Vacuum deposition
Vacuum deposition is a well-known process. It is used to deposit layers of material atom-by-atom or molecule-by-molecule on a solid surface. This process operates at pressures well below atmospheric pressure. The deposited layers can range from a thickness of one atom up to several micrometers. Many organic materials can be thermally evaporated, and consequently can form a thin film layer. The schematic illustration of the vacuum deposition process is shown in Figure 1-4.
Figure1-4: Schematic illustration of the vacuum deposition process.
The advantages of vacuum deposition technique are listed as follows:
Metal, semiconductor, insulator, and polymer can be deposited on metal, semiconductor, insulator, and even on plastic, paper…
The crystals of deposited material are related to the deposition rate, substrate temperature and the deposition angle of thermally evaporated material.
High purity films can be obtained.
III.2.2 Solution-processed deposition
Since 1990, researchers have proved that equivalent electrical performance can be obtained using solution-processed OTFTs and vacuum-processed OTFTs. Development of high performance p-type and n-type semiconductors is a key step in order to fabricate electronic devices (i.e. p-n junction devices, organic light-emitting diodes, photovoltaic, organic complementary metal-oxide-semiconductor (CMOS)). In this work, C60 and
Tips-Chapter 1: OTFTs: General Points
fabricate solution-processed OTFTs. The development of the field effect mobility of both C60
and Tips-pentacene transistors based on solution-processed OTFTs were summarized in Figure 1-5. As can be observed, the motility has been improved for both C60 and
Tips-pentacene during the past years. Table 1-2 lists the field-effect mobility (μ) values measured from OTFTs as reported in the literature, annually from 2002 through 2015.
Figure 1-5: Development of the carrier field-effect mobility of p-channel and n-channel transistors based on solution-processed OTFTs. Note that, the reported mobilities are
Year Mobility
(cm2/Vs) Material (solution-processed)
(sc) = spin coat (dc) = drop cast (dp) = dip coat (ip) = inkjet print
Solvent Ion/Ioff W/L Ref
2002 0.29 Pentacene (sc) Chloroform 2×107 100 [68] 2005 >1.5 Tips-pentacene (dc) Toluene 106 4.4 [69] 1.5 Tips-pentacene (sc) Toluene NR 5.5 [70] 0.1 C60 derivative (sc) Chlorobenze <104 4000 [71] 0.45 Pentacene (dc) Trichlorobenze 105 10 [72] 0.067 C60 derivative (sc) Chloroform 1.6×105 250 [73] 0.023 C60 derivative (sc) Chloroform 7×104 250 [73] 2007 1.2 Tips-pentacene(dc) Toluene 108 8.8 [74] 0.6 Tips-pentacene(dc) Toluene NR NR [74] 0.2 Tips-pentacene(dp) Toluene NR NR [74] 0.6 Tips-pentacene (dc) Toluene NR 10 [75] 0.48 Tips-pentacene (dc) Toluene 106 2.48 [76] 0.29 Tips-pentacene (ip) NR 107 12.5 [77] 2008 0.17 Tips-pentacene (dc) Toluene 105 2 [78] 0.15 C60 derivative (sc) Chlorobenze >106 2000 [79]
0.24 Tips-pentacene (ip) Dichlorobenze 107 39.3 [80]
0.214 Tips-pentacene (dc) Toluene 106 6.7 [81] 0.101 Tips-pentacene (dc) Chlorobenze 105 6.7 [81] 0.009 Tips-pentacene (dc) Tetrahydrofuran 104 6.7 [81] 0.018 Tips-pentacene (dc) Chloroform 104 6.7 [81] 1 Tips-pentacene (dp) Toluene 106 12.5 [82] 2009 1.2 Tips-pentacene (dc) Toluene >107 6.29 [83] 0.21 C60 derivative (sc) Trichlorobenze 5×105 NR [84] 0.001 Tips-pentacene (dc) Chlorobenze 4.3×103 25 [85]
0.06 Tips-pentacene (ip) Cyclohexanol 105 39.3 [86]
0.07 Tips-pentacene (sc) Dichlorobenze NR 30 [87] 0.3 Tips-pentacene (sc) Xylene 4×108 31.4 [88]
2010 0.8 Tips-pentacene (ip) Tetralin NR 20 [89] 2011
0.02 Tips-pentacene (ip) Toluene 104 31.7 [90]
0.72 Tips-pentacene (ip) Tetralin 109 NR [91]
0.06 Tips-pentacene (ip) Dichlorobenze 104 4.17 [92]
0.0079 Tips-pentacene (dc) Toluene 104 390 [93]
2012
11 C60 (dc) CClXylene 4 & M- 2×106 20 [94]
0.21 Tips-pentacene (ip) Anisole 4×107 15.5 [95]
1.7 Tips-pentacene (ip) Chlorobenze & Dodecane 106 4 [96]
0.85 Tips-pentacene (ip) Dichlorobenze 105 16.7 [97]
0.23 Tips-pentacene (ip) Toluene 7×105 20 [98]
0.18 Tips-pentacene (ip) NR 107 33.3 [99]
2013 0.53 Tips-pentacene (ip) polycarbonate Amorphous 1.6×106 20 [100] 0.31 Tips-pentacene (ip) Anisole 4×107 99 [101]
Chapter 1: OTFTs: General Points
Year Mobility
(cm2/Vs) Material (solution-processed)
(sc) = spin coat (dc) = drop cast (dp) = dip coat (ip) = inkjet print
Solvent Ion/Ioff W/L Ref
2015 0.073 Tips-pentacene (dc) Anisole 5×10
4 10 [102]
0.198 Tips-pentacene (ip) Dichlorobenze 8×103 6820 [103]
0.25 Tips-pentacene (ip) Anisole 8×107 NR [104]
Values for Ion/Ioff correspond to different gate voltage ranges and thus are not readily comparable to one another.
NR = Not reported
Table 1-2: Summary of field-effect mobility (μ) values measured from OTFTs based on solution-processed as reported in the literature annually from 2002 through 2015.
In this work, solution-processed deposition technique has been used to performed organic semiconductor layer. The solution-processed deposition techniques can be divided into two categories:
Fully substrate coating: the organic semiconductor solution is deposited on the whole substrate;
Selective substrate coating: the organic semiconductor solution is deposited only on specific areas.
Each technique has advantages and drawbacks that must be carefully studied in order to determine the most suitable method for this work.
Fully substrate coating Spin coating
Spin coating has been used for depositing uniform thin film in the field of micro-fabrication for several decades. Briefly, a little amount of material is deposited on the the substrate center. Then, the substrate rotates at a high speed and centrifugal forces induce material spreading uniformly on the substrate. The schematic illustration of a spin coating process is shown in Figure 1-6.
Figure 1-6: Schematic illustration of the spin coating process.
There are many factors which have a strong effect on the film morphology: the rotational velocity, the acceleration, the time, the viscosity, the concentration of the solution and the nature of the solvent (boiling point, surface tension…). Note that, in the case of organic semiconductor, it is well known that grain size is small because of a fast solvent evaporation [105].
Dip coating
Dip coating has been widely used in industry. It allows the formation of uniform layer, especially on a flat or cylindrical substrate. A typical process involves immersing the substrate into coating material solution at a constant speed, after a while, pulling up the substrate from the solution with a constant speed. A thin film of solution remains on the substrate. Then, the solvent evaporates, and consequently, the thin film is deposited. The schematic illustration of a dip coating process is shown in Figure 1-7.
Chapter 1: OTFTs: General Points
The immersion time, the speed of pulling, the solvent nature etc. have influence on the thickness and the morphology of the thin film.
Spray coating
Spray coating has been used to fabricate organic semiconductor thin films for large-area devices. The material is mixed with a neutral gas and expelled from a nozzle to a substrate. Then, droplet spreads, the solvent evaporates, and the droplet dries. The schematic illustration of a spray coating process is shown in Figure 1-8.
Figure 1-8: Schematic illustration of the spray coating process.
The thickness of the thin film is governed by the gas pressure, spray distance between nozzle and substrate, the solution concentration, the solvent material etc.
Selective substrate coating Drop casting
A droplet of organic semiconductor solution is deposited on the substrate using micropipettes (manually or automatically). This deposition method allows more time for semiconductor drying than the techniques described previously. As a consequence higher degree of organic semiconductor crystallinity can be obtained, which has a great influence on its electrical behavior [105].
The liquid volume ranging from 0.5 to 5 µl, depending on the requirement, consequently can cover several transistors at the same time as shown in Figure 1-9. This method is well adapted to a systematical study of organic semiconductor experimental parameters (solvents choice, drying and annealing temperature...) and consequently evaluates their impact on OTFT behavior. Moreover, as shown in Figure 1-9, it saves process time and
materials cost due to the fact that multiple experiments can be performed on the same substrate.
Figure 1-9: Schematic illustration of the drop casting process.
However, this deposition method suffers from a huge drawback: it is difficult to fabricate circuit due to the fact that the drop casted semiconductor covers a large surface (several mm²) and the accuracy is difficult to control.
Inkjet printing
Inkjet printing process is similar to drop casting but the volume range is smaller (some pL). As a consequence, the droplet can be addressed only on one transistor as shown in Figure 1-10.
Figure 1-10: Schematic illustration of the inkjet printing process.
Note that, the working principle of inkjet printing will be discussed in more detailed in chapter 3.
Chapter 1: OTFTs: General Points
IV Basics and structures of OTFTs
IV.1 Basics of OTFTs
Here a p-type organic semiconductor is used as an example in order to describe the basic operation and parameter extraction of OTFT.
OTFT working principle is similar to conventional field-effect transistors, where the channel carriers are induced in the channel by a gate bias.
Under a negative voltage on the gate (VGS), holes are induced and gathered in the
active layer close to the interface between insulator layer and active layer. Under a negative voltage between source and drain (VDS), gathered holes in active layer are drifted, forming
current (IDS). Both VGS and VDS can control the current.
Grain boundary and impurity inside the organic semiconductor can trap electrons. A conducting channel can be formed between source and drain only when VGS is larger than VTH.
Indeed, electrons traps filled and enough electrons gathered in active layer. Here, VTH is
defined as threshold voltage of OTFTs. As VDS increases, IDS subsequently increases linearly.
This behavior is called: linear regime. In linear regime, electrons density distribution is not continuous; instead, it presents the staircase shape from source to drain. Taking VGS, VDS into account, the linear current can be approximated as equation (1.1):
(1.1)
where W and L are the channel width and length, µ is the mobility in linear regime, Ci is the
insulator capacitance per unit area, VGS is the gate voltage, and VTH is the threshold voltage. μ
is the most important parameter in OTFTs. In linear regime, μ can be calculated using equation (1.2):
(1.2)
here, gm can be calculated as equation (1.3):
(1.3)
There are two important electrical parameters to describe the electrical properties of the transistors: the subthreshold slope SS and on/off current ratio Ion/Ioff. Figure 1-11 shows a
typical transfer characteristic of a p-type OTFT. The subthreshold slope corresponds to the difference of gate voltage values when the increase of drain current is equal to one decade. The Ion/Ioff ratio presents the difference between off state and on state current.
Figure 1-11: Typical transfer characteristics of a p-type OTFT.
As VDS continues increasing, when , the voltage drop at drain
decreases to a point which it falls to zero. At this point, which occurs the drain voltage approaches the gate voltage, holes close to the drain are depleted, leading to a pinch off in the conducting channel, and IDS becomes independent of the drain bias. This regime is called
saturation regime. The saturation current can be approximated as equation (1.4):
(1.4)
μ in saturation regime can be calculated as equation (1.5):
Chapter 1: OTFTs: General Points
IV.2 Structures of OTFTs
At least four layers are required to fabricate for an OTFT. Such layers have specific properties that could be listed as follows:
Gate: It is a conductor, and usually it’s heavily doped silicon or metal material depending on the requirement. The heavily doped silicon is used as gate for processing convenience in many studies. However, the drawback of silicon gate will be explained in the following.
Insulator: Thermally grown silicon dioxide is used as insulator in most cases. Recently organic materials such as polyvinylpyrrolidone (PVP), poly (methyl methacrylate) (PMMA), polystyrene (PS) used as insulator have also been reported [106].
Drain and Source: They are also conductors, and metal is used as drain and source, normally. The main requirement for this layer is the “electrical affinity” with the semiconductor, as explained above. For instance gold is well adapted with pentacene. Moreover, this layer could be chemically modified in order to improve the properties of OTFT.
Organic semiconductor: As listed in Table 1-1, many materials have been reported used as organic semiconductor.
Many combinations between those layers can be used to fabricate OTFT as shown in Figure 1-12. Each structure has advantages and drawbacks. In this section, four common structures will be described including their advantages and drawbacks. Structure specificity is necessary to define which one is the most convenient structure for the considered applications.
In order to classify the structures a well-known classification in “TFTs community” has been followed. For instance, if the gate is under dielectric and the drain/sources electrodes are under the semiconductor; the structure is called: bottom-gate and bottom contact.
Figure 1-12: Common OTFTs structure. (a) Back-gate and bottom-contact, (b) Bottom-gate and bottom-contact, (c) Top-gate and bottom-contact, and (d) Bottom-gate and top-contact.
The most commonly used structure is the back-gate and bottom-contact type as illustrated in Figure 1-12(a). The heavily doped silicon substrate is used as gate due to the advantage that it is easily “processable” (less processing steps are required) and SiO2 as
insulator can be thermally grown. This well-known dielectric allows obtaining a good interface between the gate and the insulator. Indeed, a smooth interface between SiO2 and the
semiconductor is also performed. In contrary, drawbacks could also be listed. As the same gate voltage is applied to the overall substrate, circuits which requiring individually addressed transistors can't be achieved. Moreover, a huge overlap between gate and drain/source electrodes is obtained that negatively impact OTFT electrical behavior. As consequence, this structure is not suitable to optimize OTFT electrical behavior. This work will not deal with this structure.
A bottom-gate and bottom-contact type OTFT is shown in Figure 1-12 (b). Different from the previous one, this structure uses a patterned gate electrode, resulting in significant reduction of overlap capacitance. Besides, many substrates can be considered such as glass, plastics… Moreover, polymeric insulator can be used. Solvent compatibility among layers is the main concern for inkjet printed transistors, i.e. the deposited layers can be re-dissolved by subsequent printing if non-orthogonal solvent were used. Thus, this structure is favorable for printing process, as semiconductor is printed at last, avoiding solvent “attack” from other
Chapter 1: OTFTs: General Points
Structures shown in Figure 1-12 (c) and (d) are often used because it is reported that their electrical characteristics is improved compare to the other OTFT configurations [107]. However, because of processing conditions those structures have not been used in this work (i.e., inkjet printing). The structure of Figure 1-12 (c) is challenging in terms of process integration, as the semiconductor layer is deposited as the second layer. The subsequent printing and heating steps can potentially degrade the semiconductor.
Fig 1-12 (d) shows that drain and source electrodes are deposited at the last process step. Patterning such electrodes can be obtained using two techniques: lithography or shadow masking. Lithography techniques needs solvent that is not required for the reasons described previously. Using shadow masking does not offer the possibility to align source-drain and gate accurately.
In this work, the bottom-gate and bottom-contact structure is used to fabricate solution processed OTFTs. The following strategy should be adopted:
Determining the best experimental parameters of organic semiconductor deposition. Drop casting method has been used to optimize experimental parameters due to the fact that it is the most convenient method to achieve systematic study. Lithographical structure has been used to optimize experimental parameters due to its reproducibility. As a consequence, “photo-patternable” but also printable polymeric insulator should be used. Optimizing bottom-gate and bottom-contact inkjet printing structure.
Fabricating fully-inkjet-printed OTFTs.
V Characteristics and parameters extraction of OTFTs
V.1 Characteristics of OTFTs
V.1.1 Transfer characteristics
The transfer characteristics corresponds to the measurement of current IDS as a function
of the gate voltage VGS for a constant drain voltage VDS. Figure 1-13 presents a typical
transfer characteristic of a p-type OTFT. From this curve, “3 operation zones” of OTFT can be defined.
Figure1-13: Typical transfer characteristic of p-type OTFT on semi-logarithmic scale.
The first area shows the OTFT behavior in off state with a current (IDS=IOFF). The low
value of current is primarily due to the electrical conductivity of the active layer, which should be as low as possible in order to decrease this current. An increase of this current under an inverse gate voltage (positive in the case of p-type transistor as shown in Figure 1-13) can be observed sometimes, is due to the activation of the carriers by the reverse electric field.
The second area shows that the formation of the channel and the drain current increases rapidly with the gate voltage.
The third area shows the on state of OTFT (IDS = ION).
V.1.2 Output characteristics
The output characteristics corresponds to the measurement of current IDS as a function
of the drain voltage VDS for a constant gate voltage VGS. Figure 1-14 shows a typical output
characteristic of a p-type OTFT. This figure shows clearly the linear regime under a weak drain voltage and the saturation regime occurs when VDS becomes lager then .
Chapter 1: OTFTs: General Points
Figure 1-14: Output characteristic of a p-type OTFT.
V.1.3 Successive measurements of the transfer characteristics
The successive measurements of the transfer characteristics corresponds to the measurement of current IDS as a function of the gate voltage VGS for a constant drain voltage
VDS. The transfer curves are measured at least two times in succession. Figure 1-15 presents
typical successive measurements of the transfer characteristic for two times of a p-type OTFT.
V.1.4 Hysteresis characteristics
The hysteresis characteristics corresponds to the measurement of current IDS as a
function of the gate voltage VGS for a constant drain voltage VDS . The measurement of the
transfer characteristic is performed when gate voltages increases then when it decreases. The difference between these two curves is called hysteresis. Figure 1-16 shows a typical hysteresis characteristic of a p-type OTFT. A difference is observed between these two curves.
Figure 1-16: Hysteresis characteristic of a p-type OTFT.
The hysteresis may be related to the charge trapping and de-trapping at the interface between the active layer and the insulator layer, or in the insulator layer.
V.1.5 Bias stress characteristics
The bias stress characteristics corresponds to the measurement of current IDS as a
function of the gate voltage VGS for a constant drain voltage VDS . The transfer curves are
measured under a bias stress. Applying a high gate voltage (negative voltage in a p-type OTFT as shown in Figure 1-17) during a long time can accelerate the test of reliability of OTFT. Figure 1-17 presents a typical successive bias-stress characteristic of a p-type OTFT.
Chapter 1: OTFTs: General Points
Figure 1-17: Bias stress characteristic of a p-type OTFT.
Gate bias-stress often induces threshold voltage shift mainly due to defect creation in semiconductor and charge trapping in insulator layer.
V.1.6 Gate leakage current characteristics
The gate leakage current characteristics corresponds to the measurement of current IGS
as a function of the gate voltage VGS for a constant drain voltage VDS. Figure 1-18 presents a
typical gate leakage current characteristic of a p-type OTFT.
In conclusion, the stability of OTFT is related to the successive transfer characteristics, hysteresis, bias-stress and gate leakage current characteristics.
V.2 Parameters extraction of OTFTs
Threshold voltage VTH, transconductance gm, subthreshold slope SS and Ion/Ioff ratio
can be obtained using the transfer characteristics. As shown in Figure 1-19 (a), by plotting the drain current IDS as a function of gate voltage VGS in the linear coordinate, the threshold
voltage VTH is typically defined as the X-intercept of the tangent line extrapolated in linear
regime of the IDS-VGS curve. The transconductance gm is the maximum value of the slope of
IDS-VGS curve (the extraction is shown in Figure 1-19 (b)). SS is defined as the maximum
slope of the log(IDS)-VGS curve, with the unit of volt-per-decade (V/Dec) (the extraction is
shown in Figure 1-19 (c)). Ion/Ioff is defined by the ratio of the maximum current divided by
the minimum current observed in the transfer characteristics (the extraction is shown in Figure 1-19 (d)).
Figure 1-19: Parameters extraction from a p-type OTFT. (a) Extraction of VTH, (b) Extraction of gm, (c) Extraction of SS, and (d) Extraction of Ion/Ioff.
Chapter 1: OTFTs: General Points
VI Thesis organization
Solution-processed OTFTs are promising technique for the fabrication of electronic devices on a very low cost and large area substrate like paper. The focus of this thesis concerns using inkjet-printing in order to fabricate high electrical performance and better stability OTFTs on flexible substrates.
In the first chapter, the development of OTFT is introduced. The principle and deposition methods including vacuum deposition and solution processing of organic semiconductor are described. Afterwards, a brief description of solution-processed OTFTs is given: the basics, the structure, the characteristics and parameters extraction of OTFTs are detailed.
The second part of this thesis consists in optimizing inkjet-printing parameters of organic semiconductor materials deposition by using drop-casting method. First, issues of solution processing, including solvent effect, drying and annealing temperature effect, and SAMs effect are presented. N-type and p-type OTFTs will be discussed in detail. Depending on the issues of solution processing mentioned in the first chapter, solvent effect, drying and annealing temperature effect, and SAMs effect will be presented to optimize parameters.
Chapter 3 describes inkjet-printing technology in order to fabricate fully-solution-processed OTFTs. In this chapter, introduction of printed electronics is firstly presented, including inkjet print technique and methodology. Then the printability of OTFT functional materials is discussed. OTFTs are fabricated using inkjet printing, and electrical characteristics are presented.
Chapter 4 describes a method in order to improve the performance of solution-processed OTFTs. In this chapter, a polymeric gate insulator functionalized with 1-aminoanthraquinone is presented in order to achieve “a better interface”, and to improve the electrical performance, including OTFTs stability. Four main factors at the semiconductor-insulator interface are measured to confirm the improvement. Electrical characterization and bias stress measurement are extracted.
Reference
[1] H. Klauk, Organic Electronics: Materials, Manufacturing and Applications, Stuttgart, Germany, Wiley-VCH, (2006)
[2] J. E. Lilienfeld, “Method and apparatus for controlling electric current”, US Patent 1,745,175, (1925).
[3] D. Kahng, “Electric field controlled semiconductor device”, US patent 3, 102, 230, (1963).
[4] M. Pope, C.E. Swenberg, Electronic Processes in Organic Crystals and Polymers, Oxford University Press, New York, (1999)
[5] G,Horowitz, X. Z. Peng,D. Fichou, F. Garnier, “The oligothiophene-based field-effect transistor: How it works and how to improve it”, J. Appl. Phys., 67, 528 (1990).
[6] H. Letheby, “On the production of a blue substance by the electrolysis of sulphate of aniline,” J. Chem. Soc., 15, 161(1862).
[7] A. Pochettino, A. Sella, “Photoelectric behavior of anthracene,” Atti Acad. Lincei, 15, pp. 355(1906).
[8] J. H. Burroughes, C. A. Jones, and R. H. Friend, “New semiconductor device physics in polymer diodes and transistors,” Nature, 335, 137 (1988).
[9] J. A. Pople, S. H. Walmsley, “Bond alternation defects in long polyene molecules,”
Molecular Phys., 5(1), 15(1962).
[10] T. Ito, H. Shirakawa, S. Ikeda, “Thermal cis-trans isomerization and decomposition of polyacetylene,” J. Pol. Sci. Pol. Chem, 13(8), 1943 (1975).
[11] A. Tsumura, K. Koezukam T. Ando, “Macromolecular electronic device: Field-effect transistor with a polythiophene thin film”, Appl. Phys. Lett., 49(18), 1210 (1986).
[12] A. Tsumura, H. Koezuka, Y. Ando, “Polythiophene field-effect transistor: Its characteristics and operation mechanism”, Synth. Met., 25(1), 11 (1988).
[13] G,Horowitz, D. FFichou, X. Z. Peng, Z.G. Xu, F. Garnier, “A field-effect transistor based on conjugated alpha-sexithienyl”, Solid State Commun., 72(4), 381 (1989).
[14] G,Horowitz, X. Z. Peng,D. Fichou, F. Garnier, “The oligothiophene‐ based field‐ effect transistor: How it works and how to improve it”, J. Appl. Phys., 67, 528 (1990).
