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Optimization of Monte Carlo Neutron Transport Simulations with Emerging Architectures

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Academic year: 2021

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Figure 2.1: Computer architectures.
Figure 2.2: Modern memory hierarchies composed of register, cache and memory.
Figure 2.3: Hardware-level parallelism where T is thread, C is core, MC is memory controller.
Figure 2.5: The ring organization of a Knights Corner coprocessor [32].
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