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Design Productivity of a High Level Synthesis Compiler versus HDL

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Academic year: 2021

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Figure

Fig. 1. Example of a trade-off radar chart with implementation quality and design efficiency parameters.
Fig. 2. Signal flow of an HEVC interpolation filter for horizontal shift of 1/4, 1/2 or 3/4 of a pixel.
Fig. 4. Example of a graph description in CAPH.
Fig. 5. Design efficiency and implementation quality chart (the smaller the better) for each filter in CAPH (clear red) and VHDL (dark blue).

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