Design Space Exploration of Optical Interfaces for Silicon Photonic Interconnects

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Design Space Exploration of Optical Interfaces for

Silicon Photonic Interconnects

Olivier Sentieys, Johanna Sepúlveda, Sébastien Le Beux, Jiating Luo, Cedric

Killian, Daniel Chillet, Ian O ’Connor, Hui Li

To cite this version:

Olivier Sentieys, Johanna Sepúlveda, Sébastien Le Beux, Jiating Luo, Cedric Killian, et al.. Design

Space Exploration of Optical Interfaces for Silicon Photonic Interconnects. 2th International Workshop

on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop), co-located with

IEEE/ACM Design Automation and Test in Europe (DATE’16), Mar 2016, Dresden, Germany.

�hal-01293506�

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http://inl.cnrs.fr http://www.inria.fr 1

Design Space Exploration of Optical

Interfaces for Silicon Photonic

Interconnects

Olivier Sentieys

1 _{, Johanna Sepúlveda}

1 _{, Sébastien Le Beux}

2 _{, Jiating Luo}

1 _,

Cedric Killian

1 _{, Daniel Chillet}

1 _{, Ian O’Connor}

2 _and

Hui Li

2

2 _{Institut des Nanotechnologies de Lyon}

Ecole Centrale de Lyon

France

1 _{INRIA, IRISA}

University of Rennes

France

(3)

http://inl.cnrs.fr http://www.inria.fr 18-mar-16 2

Context: Evolu-on of the number of cores

2005

2003

Intel,

Polaris,

80 cores

Tilera 64

TILE-Gx72

TILE-Gx100

Single-chip Cloud

Computer,48 cores

CELL

2001

2007

2009

2011

MPPA,256 cores,

28nm,2012

N

u

mb

er

of c

or

es

2013

2015

year

Source: Moustafa Mohamed, et al.,

CODE-ISSS’11.(slides)

•  Multi-cores + Data intensive applications (memory

accesses, data exchanges)

•  è high requirement for data communication

(4)

Context: Op-cal interconnect

Source: G. Kurian, et al., PACT, 2010

•  Silicon Photonics

•  High throughput:

Wavelength Division

Multiplexing, WDM

•  Lower dynamic energy

•  Lower latency

•  Multi-cores + Parallel applications + memory needs + …

•  è high requirement for data communication

•  Classical NoC

•  Need for more efficient communication infrastructure

•  Optical NoC could be a solution

•  We need design space exploration, in particular for Optical interface !!

è bottleneck !!

(5)

Context: Needs for Design Methodologies

1-models

2-simulations

3-exploration

Key enabler:

Design

methodologies

Key enabler:

Emerging

technologies

_DGFET

_{Silicon photonics}

_3D

Easily

programmable and

power efficient

processors

Focus of Design Space Exploration for 2 parts of the interface

•  channel allocation

(6)

Outline

• Context and problematic

• DSE of waveguides and wavelengths

allocation

• DSE of laser power management

(7)

Silicon Photonics Interconnects

Rx

Tx

TSV ONI: Optical Network Interface Electrical layer IP core / cluster Control network Op-cal layer Waveguide Router Chameleon Router

Electrical router

Source: •  C. Sciancalepore, et al. IEEE Photonics journal. 2012. •  Markus-ChrisAan Amann and Werner Hofmann. IEEE journal of Selected Topics in Quantum Electronics , 2009.

Photodetectors

Z. Li et al. 2008

λ

_n

λ = λ

n

λ ≠ λ

n

P

_drop

P

_crossing

Micro-resonators

CMOS-compatible VCSEL

(8)

http://inl.cnrs.fr http://www.inria.fr 18-mar-16 7 TSV ONI: Optical Network Interface Electrical layer IP core / cluster Control network Op-cal layer Waveguide Router

Communica-on schemes

Router ONIb Router ONIc

a

ONIa

ONIb

ONIc

Req λ1

NACK

Req λ2

ACK

Transmission

IP source

IP target

b

c

ONIa Router Router

(9)

Channel size design tradeoﬀ

Router

REQ

0 t₁ t₂ t₃ t₄ t₅ t₆ t₇ t₈ t

Channel size:

number of

waveguides and

wavelengths per

request, i.e.

bandwidth

data transfer time (optical domain)

versus

request latency (electrical domain)

(10)

Simula-on parameters

q

 

Models based on Gem5

q

 

Quasi-cycle accurate simulator

q

 

Integration of C++ models of optical components

q

 

Based on Garnet NoC

q

 

Simulation characteristics

q

 

Ring-based optical interconnection

q

 

8-tiles (ARM, 4-KB L1 cache) 32 bits channel width

q

 

2 architectures :

q

 

4 waveguides, 16 wavelengths for each waveguide

q

 

16 waveguides, 16 wavelengths for each waveguide

q

 

Modulation speed: 10Gb/s

(11)

Network size

Channel size

(wg,wl)

4 waveguides

16 waveguides

Area

(um

2

₎

Power

_(mW)

_(um

Area

2

₎

Power

_(mW)

(16,16)

NA

6292

2.09 (8,16)

NA

6629

2.21 (4,16)

6292

2.09 7304

2.45 (2,16)

6629

2.21 8781

2.95 (1,16)

7304

2.45 13538

4.45 (1,8)

8781

2.95 17022

5.06 (1,4)

13538

4.45 21385

5.33 (1,2)

17022

5.06 30110

5.86 (1,1)

21385

5.33 47560

6.92

Controller Synthesis Results

q

 

28nm FSDOI technology (Synopys Design Vision environment)

S

im

pl

e

co

n

tr

ol

le

rs

M

or

e

co

m

pl

ex

co

n

tr

ol

le

rs

(12)

Results: SPLASH-2 benchmark

Best channel size: 1 waveguide, 8 wavelengths

Sepuulveda15] Communication Aware Design Method for Optical Network-on-Chip

J.Sepúlveda, S.Le Beux, J.Luo, C.Killian, D.Chillet, H.Li, I.O’Connor, O.Sentieys

(13)

Outline

• Context and problematic

• DSE of Waveguides and wavelengths

allocation

• DSE of laser power management

(14)

Op-cal layer

Impact of the waveguide sharing

optical interconnect

Laser source

λ

₀

Laser source

λ

₁

Target photodetector

1

0

1 SNR

1

0

1 SNR

q

 

Communication between 2 pairs of Ips

q

 

One wavelength for each communication

q

 

No conflict between communications

q

 

Laser power at nominal value

IP

_i

IP

j

IP

_m

IP

_n

1

0

1

0

1

(15)

Op-cal layer

Impact of the waveguide sharing

optical interconnect

Laser source

λ

₀

Laser source

λ

₁

Target photodetector

q

 

Communication between 2 pairs of Ips

q

 

One wavelength for each communication

q

 

Temporal and spatial conflicts in the waveguide

q

 

Laser power at nominal value

q

 

SNR

î BER

ì

IP

_i

IP

_j

IP

_m

IP

_n

1

0

1

0

1 SNR

1

0

1

0

1 SNR

(16)

Op-cal layer

Impact of the waveguide sharing

optical interconnect

Laser source

λ

₀

Laser source

λ

₁

Target photodetector

SNR

1

0

1

0

1

0

1

0

1 q

 

How can we manage SNR and BER ?

q

 

Laser power can be ì

q

 

SNR

ì BER

î

IP

_i

IP

_j

IP

_m

(17)

Op-cal layer

Impact of the waveguide sharing

optical interconnect

Laser source

λ

₀

Laser source

λ

₁

Target photodetector

1

0

1

0

1 SNR

1

0

1

0

1 SNR

q

 

How can we manage SNR and BER ?

q

 

Laser power can be ì

q

 

SNR

ì

BER

î

q

 

Or ECC can be included in the communication channel

q

 

SNR

=

BER

î

but BW î

1

0

1

0

1

Coder Decoder

IP

_i

IP

_j

IP

_m

IP

_n

(18)

• Strategy

• How to find a good tradeoff between

• management of laser power

• introduction of codec in the channel

• Could be supported by the allocation

protocol

• req. and ack. messages can help to estimate the

loss in the optical channel

Impact of the waveguide sharing

Router ONIb Router ONIc ONIa Router Router

(19)

Outline

• Context and problematic

• DSE of Waveguides and wavelengths

allocation

• DSE of laser power management

(20)

Conclusion and future works

q

 

Optical NoC Interface design

q

 

critical issue in silicon photonics

interconnects

à

need DSE at different levels

q

 

low level DSE/management

q

 

laser power and ECC

q

 

high level DSE/management

q

 

channel allocation / allocation

protocol

q

 

Future works

q

 

tradeoff between Electric vs Optic energy

performances

q

 

on-line strategy for channel allocation

q

 

thermal aware design method

Crossbar switch Tx IP Channel Allocator Routing Arbiter Routeri Crossbar switch Rx Routeri+1 Routeri-1

(21)

http://inl.cnrs.fr http://www.inria.fr 20

Design Space Exploration of Optical Interfaces for

Silicon Photonic Interconnects

Olivier Sentieys

1

_{, Johanna Sepúlveda}

1

_{, Sébastien Le Beux}

2

_{, Jiating Luo}

1

_,

Cedric Killian

1

_{, Daniel Chillet}

1

_{, Ian O’Connor}

2

_and

Hui Li

2

Thank you !