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Equalization of Interconnect Propagation Delay with Negative Group Delay Active Circuits

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Academic year: 2021

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Fig. 5: Combination of the output gate (R S  = 90 Ω), the RLC  model line with a two-stage active NGD circuit (F 1  = F 2  =  FET EC2612, R 1  = 73 Ω and L 1  = 99  nH, R 2  = 102  Ω and L 2

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