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Comparison of Pinning Voltage Estimation Methods in Pinned Photodiode CMOS Image Sensors

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Academic year: 2021

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Fig. 1. (a) Schematic representation of a PPD pixel. The schematic potential diagrams along the cut A-A’ at equilibrium and after charge transfer are shown in (b) and (c), respectively
Fig. 3. PPD maximum electrostatic potential Φ, maximum E fn and maximum electron density Q PPD (plotted in linear and logarithmic scales) as a function of the injection potential applied to the FD of a PPD pixel with the TG on
Fig. 5. (a) Equivalent circuit of the test set-up used in the Sqrt. method [12]. (b) Square root of the drain to source current (I DS ) as a function of the gate to source biasing voltage V SG measured on a PPD-JFET structure (square root characteristic)
Fig. 8. (a) Equivalent circuit of the test set-up for the floating source (FS) extraction method discussed in [14]
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