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Low-cost countermeasures against physical attacks on cryptographic algorithms implemented on altera FPGAs

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Academic year: 2021

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Table 2.2: Doubling Attack principle Iteration i k i Q 1 = [k].P Q 2 = 2.[k].P 1 1 2 ∗ 0 2 ∗ 0 0 + P 0 + 2P 2 0 2 ∗ P 2 ∗ 2P 2P + P 4P + 2P 3 0 2 ∗ 2P 2 ∗ 4P 4P + P 8P + 2P 4 1 2 ∗ 4P 2 ∗ 8P 8P + P 16P + 2P 5 1 2 ∗ 9P 2 ∗ 18P 18P + P 36P + 2P 6 1 2 ∗ 19P 2
Table 4.1: Example of SDF timing information for a given instance_name gate.
Table 4.4: Extract of nodes classification for S-Box 5.
Figure 4.8: Experimental covariance between the power traces and a regular net (left – no
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